Abstract: The present disclosure provides a system for processing ultramafic material. The system may comprise a reactor for accelerating weathering of said ultramafic material. The reactor may comprise one or more chambers comprising one or more microbes, biological medicators, or enzymatic accelerants to facilitate the weathering of the ultramafic material.

Abstract: Apparatus (1) and corresponding method for measuring a current (10) in which a charge integrating circuit (2) integrates charge from the current to be measured (10) and applies a resulting change in voltage to a comparator circuit (4) that compares the input voltage (12) with a threshold voltage level (Vthreshoid) and provides an output (14) responsive thereto to a logic circuit (6) that generates a feedback signal (16) dependent upon the comparator output (14) and provides the feedback signal (16) to the charge integrating circuit (2) that integrates charge from the received feedback signal (16) in opposition to the integrating of the charge from the current to be measured (10). The logic circuit (6) generates an output signal (18), based upon the comparator circuit output (14) and dependent upon the level of the current to be measured (10), for example a pulse (50) of a width (TOUT) dependent upon the level of the current (10).

Abstract: An active matrix display has a column driver for providing signals to the pixels for driving the display elements, the column driver comprising digital to analogue converter circuitry providing a first number of display element drive levels. Within each pixel, the first number of display element drive levels is converted into a second, greater number, of pixel grey levels. This combines multi-level digital to analogue conversion with in-pixel level generation and enables the complexity of the DACs to be reduced so that they can be integrated onto the display substrate, for example using low temperature polysilicon processing.

Abstract: An amplification circuit comprises a capacitor arrangement (42) and a switching arrangement. The capacitor arrangement has a first capacitor (C2) which has a voltage-dependent capacitance and a second capacitor (C1) (which may also be voltage-dependent). The circuit is operable in two modes, a first mode in which the input voltage is provided to one terminal of at least the first capacitor, and a second mode in which the switching arrangement causes charge to be redistributed between the first and second capacitors such that the voltage across the first capacitor changes to reduce the capacitance of the first capacitor, the output voltage being dependent on the resulting voltage across the first capacitor. The invention uses a voltage controlled capacitance in combination with charge sharing between capacitors, which has the result of providing a voltage amplification characteristic. This arrangement can thus be used for the amplification of an analogue voltage, or the boosting of a fixed level (i.e.

Abstract: In a digital to analogue converter, a plurality of digital inputs are used to select one of first and second binary voltage levels as binary inputs (10) to the converter. A capacitor circuit (C, 2C, . . . , 32C) is associated with each input, and these are controlled to output an effective voltage to an output load comprising the first binary voltage level, the second binary voltage level or an average of the first and second binary voltage levels in dependence on the bits of the digital input word. The plurality of capacitor circuits can be operated in either a voltage divider mode (to provide an average output) or a resistor mode depending on the value of the digital data. Operation of the capacitor circuits in this way can result in a reduction in the currents flowing and can therefore reduce the power consumption.

Abstract: In an active matrix display device, such as AMLCD, having an array of pixels (P) addressed via sets of row and column conductors (14, 15) to which, respectively, selection and data signals are applied, each pixel comprises a plurality of sub pixels (P1-P4) which each have an associated switch, for example a TFT, (T1-T4) and which are addressed with data signals through a common switch (T1) coupled to a column conductor (15). Addressing the sub pixels through a common switch reduces the effective capacitance of the column conductor.

Abstract: An active matrix array device has a plurality of matrix array elements (100), each of which have a first capacitive device (120) coupled to a charging conductor (32m) via a first switch (100) being responsive to an addressing conductor (22n). In addition, the matrix array elements (100) comprise a second capacitive device (130) coupled to the first capacitive device (120) via a second switch (112) being responsive to en enable signal provided via an enable conductor (42n). The second capacitive device (130) is coupled to the control terminal of a third switch (114), which is coupled between the first capacitive device (120) and a potential source like the charging conductor (32m). The second capacitive device (130) is used to sample the voltage across the first capacitive device (120), which enables the third switch (114) if of an appropriate value, thus providing a conductive path between the first capacitive device (120) and the potential source.

Abstract: In a digital to analogue converter, a plurality of digital inputs are used to select one of first and second binary voltage levels as binary inputs (10) to the converter. A capacitor circuit (C, 2C, . . . , 32C) is associated with each input, and these are controlled to output an effective voltage to an output load comprising the first binary voltage level, the second binary voltage level or an average of the first and second binary voltage levels in dependence on the bits of the digital input word. The plurality of capacitor circuits can be operated in either a voltage divider mode (to provide an average output) or a resistor mode depending on the value of the digital data. Operation of the capacitor circuits in this way can result in a reduction in the currents flowing and can therefore reduce the power consumption.

Abstract: A display device, for example a liquid crystal display device (1), and driving method are provided that avoid the need to provide the display device with display data (e.g. video) containing individual display settings for each pixel. The display device comprises an array of pixels (21-36, 71a-79d, 121-136) and an array of processing elements (41-48, 71-79, 141-148), each processing element being associated with a respective pixel or group of pixels. The processing elements (41-48, 71-79, 141-148) perform processing of compressed input display data at pixel level. The processing elements (41-48, 71-79, 141-148) decompress the input data to determine individual pixel settings for their associated pixel or pixels. The processing elements (41-48, 71-79, 141-148) then drive the pixels (21-36, 71a-79d, 121-136) at the individual settings. A processing element may interpolate pixel settings from input data allocated to itself and one or more neighbouring processing elements.

Abstract: A method of controlling an active matrix LCD involves providing a pixel drive signal to each pixel for storage on the pixel for a first period of time and providing a second drive voltage to each pixel for a second period of time, wherein the durations of the first and second periods of time are controlled to vary the pixel light output. In this method, each pixel is driven in two stages. For the first stage, the pixel data voltages remain constant, and in the second stage a different voltage is applied to the pixels. The light output from the pixels is modified by altering the durations of the two stages. This avoids the need for additional adjustable voltage sources to enable compensation for temperature and other conditions.

Abstract: Apparatus (1) and corresponding method for measuring a current (10) in which a charge integrating circuit (2) integrates charge from the current to be measured (10) and applies a resulting change in voltage to a comparator circuit (4) that compares the input voltage (12) with a threshold voltage level (Vthreshoid) and provides an output (14) responsive thereto to a logic circuit (6) that generates a feedback signal (16) dependent upon the comparator output (14) and provides the feedback signal (16) to the charge integrating circuit (2) that integrates charge from the received feedback signal (16) in opposition to the integrating of the charge from the current to be measured (10). The logic circuit (6) generates an output signal (18), based upon the comparator circuit output (14) and dependent upon the level of the current to be measured (10), for example a pulse (50) of a width (TOUT) dependent upon the level of the current (10).

Abstract: A method of controlling an illumination source for a display device comprises using an integrated light sensor (14) to detect a light level when the illumination source (12) and light sensor are driven with first drive conditions and using the integrated light sensor to detect a light level when the illumination source (12) and light sensor are driven with second drive conditions, different to the first drive conditions. The first and second detected light levels are processed to derive a first value representing the ambient light level and a second value representing the illumination source output level. This method uses at least two light sensor measurements to derive information concerning both the ambient light levels and the illumination source output level for known drive conditions. This then enables the display device to be controlled taking into account the ambient light level and taking into account the output characteristics of the illumination source.

Abstract: An active matrix display device, such as an AMLCD, having sets of row and column address conductors (18, 19) connected to a row and column array of picture elements (12) and drive means (21, 23, 25) for supplying selection and data signals to the sets of rows and column address conductors respectively uses a plurality of serial charge redistribution digital to analogue conversion means (30) to convert multi-bit digital data signals supplied to the column address conductors (19) into analogue voltage levels for use by the picture elements. Each conversion means uses the capacitances of two column address conductors between which charge is shared by operation of conversion switches (31). The drive means is arranged to supply data signals alternately to the two column address conductors of each conversion means. This leads to a reduction in conversion errors and consequential unwanted display artefacts.

Abstract: An electronic device has a first active matrix pixel array device (52) and a second pixel array device (54). The first and second pixel arrays are provided on separate substrates (56,58), and a part (62) of the addressing or processing circuitry of the first active matrix array device (52) is provided on the substrate (58) of the second pixel array. The invention provides the distribution of control circuitry between two substrates (56,58) in a device having two array devices (52,54). This can enable the costs associated with a defect in the row and column driver circuitry to be minimised.

Abstract: A display device with capacitive display pixels, in which a drive scheme is used for capacitive coupling of voltages to enable reduced column voltage swings to be obtained. Each pixel has two storage capacitors. The use of two storage capacitors provides some freedom in the choice of the magnitude of the voltage swing provide on one terminal of one of the storage capacitors. The first capacitor (C1) of all pixels of the display may be grounded, and only the second capacitor (C2) is subjected to changes in voltage to be capacitively coupled to the display cell. This provides a flexible capacitor line drive type scheme.

Abstract: An active matrix device includes a plurality of display elements 10 including a data storage node 18, 72 for storing data in the form of charge on a capacitor 72 and/or capacitative element 18. Refresh circuitry 51 is provided to refresh the data storage node, for example including temporary storage circuit 55 and drive circuit 56.

Abstract: An active matrix display device comprises an array of picture elements, e.g. liquid crystal picture elements, first and second sets of address conductors (16, 18) extending in row and column directions respectively and connected with the picture elements, and a set of connection conductor lines (30?) extending in the same direction as one set of address conductors (18), each of which is connected to a respective one of the other set of conductors (16), and via which address signals are supplied to that other set. To avoid unwanted display artefacts, each connection conductor line (30?) extends from one side of the array and terminates adjacent its connection point (32) to its associated address conductor (16) and a respective complementary conductor line (30?) is provided which extends from close to the connection point (32) to the opposite side of the array, the complementary conductor line being electrically separate from the connection line (30?) and coupled to reference signal supply (40).

Abstract: An active matrix array device, such as an AMLCD, has an array of matrix elements (10) addressed via sets of address conductors (14, 16). An address circuit (35) connected to one set (16) comprises a multiplexing circuit (31) integrated on the same substrate (25) as the matrix elements which has a plurality of signal bus lines (33), the one set of address conductors being organized in groups with each conductor in a group being associated with a respective and different signal bus line and the groups being addressed in sequence. Each signal bus line is connected to a respective signal processing circuit (42), e.g. a D/A converter or sample and hold circuit in the case of an AMLCD, which is also integrated on the substrate. To avoid problems in use due to the manner of fabrication of these circuits and the operation of the multiplexing circuit, the address circuit is arranged so that the individual signal processing circuits associated with adjacent column conductors are located close together on the substrate.

Abstract: Magnetoresistive random access memory (MRAM) is used to provide in-pixel memory circuits for display devices. A memory circuit (25) comprises memory elements, for storing a drive setting, and a read-out circuit, for example a flip-flop circuit (64), for reading-out the stored drive setting. The memory elements comprise two MRAMs (60, 62), each coupled to a respective input of the flip-flop circuit (64). A drive circuit (26) is coupled to the read-out circuit and a pixel display electrode (27) for driving the pixel display electrode (27) dependent upon the read-out drive setting with drive current that does not pass through the MRAMs (60, 62). A display device (1) is provided comprising a plurality of pixels (20) each associated with one such memory circuit (25) and drive circuit (26).

Abstract: A pixellated device (10), such as a display, has pixel row and column address lines (18,20) for addressing each pixel, thereby providing signal data to each pixel (12) or reading signal data from each pixel. An array of memory cells (22) is provided on the substrate interspersed with the pixel drive circuitry (16), wherein memory address circuitry (24,26,28,30) is provided enabling data to be written to each memory cell and enabling data to be read from each cell (22), independently of the signal data. Each memory cell (22) is thus addressable independently of the pixel data. Thus, the memory cells do not form part of the pixel circuitry, which allows the memory to be used in a flexible manner. For example, the memory may be used for purposes not directly associated with the driving or addressing of the pixels of the device.