Abstract: A cascaded analog-to-digital converter includes a first stage delta-sigma modulator to quantize an input signal and produce a first quantization error signal. A second, coupled multi-stage delta-sigma modulator quantizes less significant bits of the input signal, wherein a first quantization stage is coupled to the first quantization error signal to quantize the next most significant bits of the input signal and produce a second quantization error signal. A second quantization stage is coupled to the second quantization error signal to quantize the least significant bits of the input signal and produce a third quantization error signal. A noise-shaping filter is coupled to the third quantization error signal, the output of which is subtracted from the first quantization error signal to produce said input of the first quantization stage.

Abstract: Methods and circuit embodiments are disclosed for implementing an improved signal path for a sample-and-hold output. In exemplary embodiments, a sample-and-hold signal path for use in a pipelined ADC includes a sample-and-hold circuit configured to operate in two distinct phases. The sample-and-hold circuit includes an input node, an output node, and a power supply node. The power supply node is configured to power down the op amp during one phase and power up the op amp during the other phase. The sample-and-hold stage is configured to provide output during one phase only. Other aspects of the invention include embodiments in which a sample-and-hold stage signal path in a pipelined analog-to-digital converter is configured to accommodate a plurality of parallel outputs.

Abstract: System and method for improved time-interleaved analog-to-digital converter arrays which reduces sampling mismatch distortion found in prior art arrays. There may be two causes of non-uniform sampling mismatch in a TI-ADC array, a mismatch due to skew and a mismatch due to clock jitter. To minimize non-uniform sampling mismatch, the mismatch due to skew can be addressed. A preferred embodiment comprises adjusting a delay imparted on the sampling clock by an adjustable delay in each channel of a plurality of channels in the TI-ADC array to minimize skew and randomly switching between two delays that span a zero-skew delay to reduce residual skew in each channel and thus eliminate (or reduce) frequency domain tones caused by non-uniform sampling mismatch.

Abstract: Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.

Abstract: Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.

Abstract: An analog-to-digital converter apparatus has a plurality of stages. Each stage includes a residue amplifier having a first and second amplifier unit. Each of the amplifier units has a first input locus, a second input locus and an output locus. The amplifier units cooperate in receiving a differential input data signal at the first input loci. A DC level setting signal unit is coupled with the second input loci and provides a DC level setting current in a first current direction. A counter-current signal generating unit is coupled with the second input loci via a single coupling locus common with the second input loci and provides a control current signal to the second input loci in a second current direction opposite to the first current direction. The control current signal provides a DC level control for each of the amplifier units.

Abstract: A circuit and method that provides a cascode current source/sink with high output impedance. In one example, the dependency on the external load is reduced by directing a compensation current corresponding to change in base current in the cascode (Q1) in an approach such that the compensation current cancels out the error of the cascode (Q1). In a further example, biasing circuitry (200) is included and arranged such that change in base current of the cascode (Q1) is detected and a corresponding current is summed at the emitter of the cascode (Q1) such that the collector current of the cascode (Q1) remains unchanged.

Abstract: A circuit and method that provides a cascode current source/sink with high output impedance. In one example, the dependency on the external load is reduced by directing a compensation current corresponding to change in base current in the cascode (Q1) in an approach such that the compensation current cancels out the error of the cascode (Q1). In a further example, biasing circuitry (200) is included and arranged such that change in base current of the cascode (Q1) is detected and a corresponding current is summed at the emitter of the cascode (Q1) such that the collector current of the cascode (Q1) remains unchanged.