Abstract: A quantum well is formed in a substrate to define a hub, ports extending from the hub, and a deflective structure in the hub. Electrons move through the hub and ports according to the ballistic electron effect. Gates control the movement of the electrons, causing them to be incident on the deflective structure on one side or the other, thus controlling the direction in which they are deflected and the port through which they pass.

Abstract: An analog-to-digital converter converts a frequency-modulated signal into a digital signal. The frequency-modulated signal is supplied to multiple comparators, such as low-pass filters, which determine whether the signal falls within their frequency ranges. The outputs of the comparators are converted into a digital output signal, e.g., by fat-tree encoding. Each comparator has a differently tuned capacitive load to cause a phase delay in the input signal. When the phase-delayed and non-phase-delayed signals are supplied to a D-Flop, the phase delay is determined by whether the latch conditions are met.

Abstract: A quantum well is formed in a substrate to define a hub, ports extending from the hub, and a deflective structure in the hub. Electrons move through the hub and ports according to the ballistic electron effect. Gates control the movement of the electrons, causing them to be incident on the deflective structure on one side or the other, thus controlling the direction in which they are deflected and the port through which they pass.

Abstract: A smart card includes a power source, a processing chip, and a charge-pump subsystem for powering the processing chip. The charge-pump subsystem includes a capacitor which is connected cyclically to the power source to charge the capacitor, to the processing chip to power the processing chip, and to ground to discharge the capacitor. The charge-pump subsystem can include three such capacitors so that while one of them is charging, another is powering the processing chip, and a third is discharging. The charge-pump subsystem blocks attempts to discover a secret key in the processing chip by decorrelating power consumption from the internal operations of the processing device.

Abstract: A Procesor-In-Memory (PIM) includes a digital accelerator for image and graphics processing. The digital accelerator is based on an ALU having multipliers for processing combinations of bits smaller than those in the input data (e.g., 4×4 adders if the input data are 8-bit numbers). The ALU implements various arithmetic algorithms for addition, multiplication, and other operations. A secondary processing logic includes adders in series and parallel to permit vector operations as well as operations on longer scalars. A self-repairing ALU is also disclosed.

Abstract: A Procesor-In-Memory (PIM) includes a digital accelerator for image and graphics processing. The digital accelerator is based on an ALU having multipliers for processing combinations of bits smaller than those in the input data (e.g., 4×4 adders if the input data are 8-bit numbers). The ALU implements various arithmetic algorithms for addition, multiplication, and other operations. A secondary processing logic includes adders in series and parallel to permit vector operations as well as operations on longer scalars. A self-repairing ALU is also disclosed.