Patents by Inventor Martin Revitz
Martin Revitz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5656514Abstract: A high gain, high frequency transistor is formed having a combination of a moderately doped retrograde emitter and a collector which is formed by self-aligned implantation through an emitter opening window. This combination allows continued base width scaling and ensures high current capability yet limits the electric field at the emitter-base junction, particularly near the base contacts, in order to reduce leakage and capacitance and to enhance breakdown voltage. Cut-off frequencies on the order of 100 GHz can thus be obtained in the performance of a transistor with a 30 nm base width in a SiGe device.Type: GrantFiled: November 22, 1994Date of Patent: August 12, 1997Assignee: International Business Machines CorporationInventors: David Ahlgren, Jack Chu, Martin Revitz, Paul Ronsheim, Mary Saccamango, David Sunderland
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Patent number: 5385850Abstract: A low temperature, epitaxial, in situ doped semiconductor layer is used as a sacrificial dopant source. The resulting doped region is small-dimensioned with a tightly controlled dopant concentration. The dopant layer is oxidized in a relatively low-temperature environment, and removed by etching. The process can be used to form a vertical bipolar transistor, where the doped region is the base, and wherein portions of the oxidized dopant layer are left as insulators.Type: GrantFiled: February 7, 1991Date of Patent: January 31, 1995Assignee: International Business Machines CorporationInventors: Jack O. Chu, Chang-Ming Hsieh, Victor R. Nastasi, Martin Revitz, Paul A. Ronsheim
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Patent number: 5132765Abstract: There is provided a method for use in the fabrication of a transistor, the method including the steps of: providing a substrate of semiconductor material including a region of first conductivity type; forming a first layer of second conductivity type epitaxial semiconductor material over the region; forming a second layer of second conductivity type epitaxial semiconductor material over the first layer, the second layer of a relatively higher dopant concentration than the first layer; oxidizing a portion of the second layer; and removing the oxidized portion of the second layer to expose a portion of the first layer, the exposed portion of the first layer forming an intrinsic base region. The steps of forming the first and second layers are preferably performed using low temperature, ultra-high vacuum, epitaxial deposition processes.Type: GrantFiled: January 31, 1991Date of Patent: July 21, 1992Inventors: Jeffrey L. Blouse, Inge G. Fulton, Russell C. Lange, Bernard S. Meyerson, Karen A. Nummy, Martin Revitz, Robert Rosenberg
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Patent number: 5008207Abstract: There is provided a method for use in the fabrication of a transistor, the method including the steps of: providing a substrate of semiconductor material including a region of first conductivity type; forming a first layer of second conductivity type epitaxial semiconductor material over the region; forming a second layer of second conductivity type epitaxial semiconductor material over the first layer, the second layer of a relatively higher dopant concentration than the first layer; oxidizing a portion of the second layer; and removing the oxidized portion of the second layer to expose a portion of the first layer, the exposed portion of the first layer forming an intrinsic base region. The steps of forming the first and second layers are preferably performed using low temperature, ultra-high vacuum, epitaxial deposition processes.Type: GrantFiled: September 11, 1989Date of Patent: April 16, 1991Assignee: International Business Machines CorporationInventors: Jeffrey L. Blouse, Inge G. Fulton, Russell C. Lange, Bernard S. Meyerson, Karen A. Nummy, Martin Revitz, Robert Rosenberg
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Patent number: 4701998Abstract: A method for fabricating a bipolar transistor having a base doping variation of less than 20% is disclosed. A polysilicon base contact bipolar transistor is formed up to the point just prior to the intrinsic base-emitter formation. The intrinsic base-emitter opening is then reactive ion etched through the polysilicon base contact layer down to and into a single crystal silicon body thereunder, whereby the surface of the single crystal silicon is damaged. A silicon dioxide layer is then grown on the exposed and damaged single crystal silicon to convert the damaged silicon surface into a silicon dioxide layer. The silicon dioxide layer is removed by chemical etching to expose undamaged single crystal silicon. A screen silicon dioxide layer 50 to 500 .ANG..+-.10%, e.g., 180 .ANG., is then formed on the thus exposed undamaged single crystal silicon.Type: GrantFiled: December 2, 1985Date of Patent: October 27, 1987Assignee: International Business Machines CorporationInventors: David C. Ahlgren, Robert E. Bendernagel, Russell C. Lange, Martin Revitz
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Patent number: 4667395Abstract: A method, useful in fabricating semiconductor integrated circuits, for passivating an undercut formed by etch-back of a silicon dioxide layer under a diverse insulator film is disclosed. The method includes the step of coating the device with a thin, conformal film to a thickness sufficient only to line, without refilling, the lateral walls of the undercut region.Type: GrantFiled: March 29, 1985Date of Patent: May 26, 1987Assignee: International Business Machines CorporationInventors: David C. Ahlgren, William H. Ma, Martin Revitz
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Patent number: 4437108Abstract: A contact structure in a double polysilicon device is described in which direct shorts between overlying polysilicon conductors due to a "polysilicon void phenomenon" is overcome by patterning an appropriate etch stop between the conductors.Type: GrantFiled: December 20, 1982Date of Patent: March 13, 1984Assignee: International Business Machines CorporationInventors: James R. Gardiner, Stanley R. Makarewicz, Martin Revitz, Joseph F. Shepard
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Patent number: 4394406Abstract: A contact structure in a double polysilicon device is described in which direct shorts between overlying polysilicon conductors due to a "polysilicon void phenomenon" is overcome by patterning an appropriate etch stop between the conductors.Type: GrantFiled: June 30, 1980Date of Patent: July 19, 1983Assignee: International Business Machines Corp.Inventors: James R Gardiner, Stanley R. Makarewicz, Martin Revitz, Joseph F. Shepard
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Patent number: 4354309Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The intrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing.Type: GrantFiled: September 12, 1980Date of Patent: October 19, 1982Assignee: International Business Machines Corp.Inventors: James R. Gardiner, William A. Pliskin, Martin Revitz, Joseph F. Shepard
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Patent number: 4341009Abstract: A buried electrical contact is made to a substrate of monocrystalline silicon through a relatively thin layer of silicon dioxide without causing damage to the relatively thin layer of silicon dioxide. This is accomplished through depositing a thin layer of polycrystalline silicon over the relatively thin layer of silicon dioxide prior to forming the opening in the relatively thin layer of silicon dioxide for the electrical contact to the substrate. After the thin layer of polycrystalline silicon is deposited, an opening is formed therein so that the thin layer of polycrystalline silicon functions as a mask to etch a corresponding opening in the relatively thin layer of silicon dioxide. Then, a layer of polycrystalline silicon is deposited over the exposed surface of the substrate and the thin layer of polycrystalline silicon to form the electrical contact through the opening in the relatively thin layer of silicon dioxide to the substrate.Type: GrantFiled: December 5, 1980Date of Patent: July 27, 1982Assignee: International Business Machines CorporationInventors: Robert F. Bartholomew, Paul L. Garbarino, James R. Gardiner, Martin Revitz, Joseph F. Shepard
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Patent number: 4249968Abstract: A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing.Type: GrantFiled: December 29, 1978Date of Patent: February 10, 1981Assignee: International Business Machines CorporationInventors: James R. Gardiner, William A. Pliskin, Martin Revitz, Joseph F. Shepard
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Patent number: 4191603Abstract: In a field effect device such as a charge coupled device or field effect transistor in which at least two levels of polycrystalline silicon conductors are used; these two levels of polycrystalline silicon are isolated from one another with a dielectric layer. Disclosed is a dielectric layer of reflowed phosphosilicate glass (PSG) on top surfaces of a polycrystalline silicon layer which may be doped by phosphorous impurities diffusing from the PSG.Type: GrantFiled: May 1, 1978Date of Patent: March 4, 1980Assignee: International Business Machines CorporationInventors: Paul L. Garbarino, Martin Revitz, Joseph F. Shepard