Abstract: A precursor material for forming a film of a group IB-IIIA-chalcogenide compound and a method of making this film are disclosed. The film contains group IB-chalcogenide nanoparticles and/or group IIIA-chalcogenide nanoparticles and/or nanoglobules and/or nanodroplets and a source of extra chalcogen. Alternatively, the film may contain core-shell nanoparticles having core nanoparticles include group IB and/or IIIA elements, which are coated with a shell of elemental chalcogen material. The method of making a film of group IB-IIIA- chalcogenide compound includes mixing the nanoparticles and/or nanoglobules and/or nanodroplets to form an ink, depositing the ink on a substrate, heating to melt the extra chalcogen and to react the chalcogen with the group IB and group IIIA elements and/or chalcogenides to form a dense film.

Abstract: A precursor material for forming a film of a group IB-IIIA-chalcogenide compound and a method of making this film are disclosed. The film contains group IB-chalcogenide nanoparticles and/or group IIIA-chalcogenide nanoparticles and/or nanoglobules and/or nanodroplets and a source of extra chalcogen. Alternatively, the film may contain core-shell nanoparticles having core nanoparticles include group IB and/or IIIA elements, which are coated with a shell of elemental chalcogen material. The method of making a film of group IB-IIIA-chalcogenide compound includes mixing the nanoparticles and/or nanoglobules and/or nanodroplets to form an ink, depositing the ink on a substrate, heating to melt the extra chalcogen and to react the chalcogen with the group IB and group IIIA elements and/or chalcogenides to form a dense film.

Abstract: Methods and devices are provided for improved thermal management for photovoltaic devices and assemblies. In one embodiment, the photovoltaic device comprises of at least one photovoltaic cell based on a thin-film photovoltaic stack deposited directly onto a thermally conductive substrate. The thermally conductive substrate is connected to a heat sink in a configuration to allow sufficient heat transfer that lowers a normal operating cell temperature (NOCT) of the photovoltaic cell, thus increasing the efficiency of the cell and the module.

Abstract: Methods and devices are provided for reducing wasted space and capacity in solar module assemblies. In one embodiment, the method comprises mounting a plurality of modules onto at least one support rail to define a solar assembly segment wherein the solar assembly segment has a length of no more than about half the interior length of the shipping container used to ship the segment. The solar modules each have a weight less than about 20 kg and a length between about 1660 mm and about 1666 mm, and a width between about 700 mm and about 706 mm. In one embodiment, the length of the solar modules is limited by the longest support beam that may fit in a shipping container, which in one example is about 11,720 mm. The modules are also limited so that they can be limited to weighing no more than about 20 kg. In one embodiment, the module may be sized to provide at least 80 watts of power at AM 1.5 G. In another embodiment, the module may be sized to provide at least 90 watts of power at AM 1.5 G.

Abstract: Methods and devices are provided for improved large-scale solar installations. In one embodiment, a junction-box free photovoltaic module is used comprising of a plurality of photovoltaic cells and a module support layer providing a mounting surface for the cells. The module has a first electrical lead extending outward from one of the photovoltaic cells, the lead coupled to an adjacent module without passing the lead through a junction box. The module may have a second electrical lead extending outward from one of the photovoltaic cells, the lead coupled to another adjacent module without passing the lead through a junction box. Without junction boxes, the module may use connectors along the edges of the modules which can substantially reduce the amount of wire or connector ribbon used for such connections.

Abstract: Series interconnection of optoelectronic device modules is disclosed. Each device module includes an active layer disposed between a bottom electrode and a transparent conducting layer. An insulating layer is disposed between the bottom electrode of a first device module and a backside top electrode of the first device module. One or more vias are formed through the active layer, transparent conducting layer and insulating layer of the first device module. Sidewalls of the vias are coated with an insulating material such that a channel is formed through the insulating material to the backside top electrode of the first device module. The channel is at least partially filled with an electrically conductive material to form a plug that makes electrical contact between the transparent conducting layer and the backside top electrode of the first device module.

Abstract: Charge-splitting networks, optoelectronic devices, methods for making optoelectronic devices, power generation systems utilizing such devices and method for making charge-splitting networks are disclosed. An optoelectronic device may include a porous nano-architected (e.g., surfactant-templated) film having interconnected pores that are accessible from both the underlying and overlying layers. A pore-filling material substantially fills the pores. The interconnected pores have diameters of about 1-100 nm and are distributed in a substantially uniform fashion with neighboring pores separated by a distance of about 1-100 nm. The nano-architected porous film and the pore-filling, material have complementary charge-transfer properties with respect to each other, i.e., one is an electron-acceptor and the other is a hole-acceptor. The nano-architected porous, film may be formed on a substrate by a surfactant temptation technique such as evaporation-induced self-assembly.

Abstract: A high-throughput method of forming a semiconductor precursor layer by use of a chalcogen-containing vapor is disclosed. In one embodiment, the method includes forming a first layer of a first precursor material over a surface of a substrate, wherein the precursor material comprises group IB-chalcogenide and/or group IIIA-chalcogenide particles. The method may include forming at least a second layer of a second precursor material over the first layer, wherein the second precursor material comprises group IB-chalcogenide and/or group IIIA-chalcogenide particles and wherein the second precursor material has a chalcogen content greater than that of the first material.

Abstract: A precursor material for forming a film of a group IB-IIIA-chalcogenide compound and a method of making this film are disclosed. The film contains group IB-chalcogenide nanoparticles and/or group IIIA-chalcogenide nanoparticles and/or nanoglobules and/or nanodroplets and a source of extra chalcogen. Alternatively, the film may contain core-shell nanoparticles having core nanoparticles include group IB and/or IIIA elements, which are coated with a shell of elemental chalcogen material. The method of making a film of group IB-IIIA-chalcogenide compound includes mixing the nanoparticles and/or nanoglobules and/or nanodroplets to form an ink, depositing the ink on a substrate, heating to melt the extra chalcogen and to react the chalcogen with the group IB and group IIIA elements and/or chalcogenides to form a dense film.

Abstract: Methods and devices are provided for absorber layers formed on foil substrate. In one embodiment, a method of manufacturing photovoltaic devices may be comprised of providing a substrate comprising of at least one electrically conductive aluminum foil substrate, at least one electrically conductive diffusion barrier layer, and at least one electrically conductive electrode layer above the diffusion barrier layer. The diffusion barrier layer may prevent chemical interaction between the aluminum foil substrate and the electrode layer. An absorber layer may be formed on the substrate. In one embodiment, the absorber layer may be a non-silicon absorber layer. In another embodiment, the absorber layer may be an amorphous silicon (doped or undoped) absorber layer. Optionally, the absorber layer may be based on organic and/or inorganic materials.

Abstract: Charge-splitting networks, optoelectronic devices, methods for making optoelectronic devices, power generation systems utilizing such devices and method for making charge-splitting networks are disclosed. An optoelectronic device may include a porous nano-architected (e.g., surfactant-templated) film having interconnected pores that are accessible from both the underlying and overlying layers. A pore-filling material substantially fills the pores. The interconnected pores have diameters of about 1-100 nm and are distributed in a substantially uniform fashion with neighboring pores separated by a distance of about 1-100 nm. The nano-architected porous film and the pore-filling material have complementary charge-transfer properties with respect to each other, i.e., one is an electron-acceptor and the other is a hole-acceptor. The nano-architected porous, film may be formed on a substrate by a surfactant temptation technique such as evaporation-induced self-assembly.

Abstract: Optoelectronic device modules, arrays optoelectronic device modules and methods for fabricating optoelectronic device modules are disclosed. The device modules are made using a starting substrate having an insulator layer sandwiched between a bottom electrode made of a flexible bulk conductor and a conductive back plane. An active layer is disposed between the bottom electrode and a transparent conducting layer. One or more electrical contacts between the transparent conducting layer and the back plane are formed through the transparent conducting layer, the active layer, the flexible bulk conductor and the insulating layer. The electrical contacts are electrically isolated from the active layer, the bottom electrode and the insulating layer.

Abstract: Series interconnection of optoelectronic device modules is disclosed. Each device module includes an active layer disposed between a bottom electrode and a transparent conducting layer. An insulating layer is disposed between the bottom electrode of a first device module and a backside top electrode of the first device module. One or more vias are formed through the active layer, transparent conducting layer and insulating layer of the first device module. Sidewalls of the vias are coated with an insulating material such that a channel is formed through the insulating material to the backside top electrode of the first device module. The channel is at least partially filled with an electrically conductive material to form a plug that makes electrical contact between the transparent conducting layer and the backside top electrode of the first device module.

Abstract: One or more substrates may be coiled into one or more coils in such a way that adjacent turns of the coils do not touch one another. The one or more coiled substrates are placed in a treatment chamber where substantially an entire surface of the one or more coiled substrates may be treated with a surface treatment process. One or more spacers may be placed between adjacent layers of the coiled substrate before a full turn of the substrate has been coiled around a carousel.

Abstract: An absorber layer may be formed on on a substrate using atomic layer deposition reactions. An absorber layer containing elements of groups IB, IIIA and VIB may be formed by placing a substrate in a treatment chamber and performing atomic layer deposition of a group IB element and/or one or more group IIIA elements from separate sources onto a substrate to form a film. A group VIA element is then incorporated into the film and annealed to form the absorber layer. The absorber layer may be greater than about 25 nm thick. The substrate may be coiled into one or more coils in such a way that adjacent turns of the coils do not touch one another. The coiled substrate may be placed in a treatment chamber where substantially an entire surface of the one or more coiled substrates may be treated by an atomic layer deposition process.

Abstract: An ink for forming CIGS photovoltaic cell active layers is disclosed along with methods for making the ink, methods for making the active layers and a solar cell made with the active layer. The ink contains a mixture of nanoparticles of elements of groups IB, IIIA and (optionally) VIA. The particles are in a desired particle size range of between about 1 nm and about 500 nm in diameter, where a majority of the mass of the particles comprises particles ranging in size from no more than about 40% above or below an average particle size or, if the average particle size is less than about 5 nanometers, from no more than about 2 nanometers above or below the average particle size. The use of such ink avoids the need to expose the material to an H2Se gas during the construction of a photovoltaic cell and allows more uniform melting during film annealing, more uniform intermixing of nanoparticles, and allows higher quality absorber films to be formed.

Abstract: One or more substrates may be coiled into one or more coils in such a way that adjacent turns of the coils do not touch one another. The one or more coiled substrates are placed in a treatment chamber where substantially an entire surface of the one or more coiled substrates may be treated with a surface treatment process. One or more spacers may be placed between adjacent layers of the coiled substrate before a full turn of the substrate has been coiled around a carousel.

Abstract: The metallic components of a IB-IIIA-VIA photovoltaic cell active layer may be directly coated onto a substrate by using relatively low melting point (e.g., less than about 500° C.) metals such as indium and gallium. Specifically, CI(G)S thin-film solar cells may be fabricated by blending molten group IIIA metals with solid nanoparticles of group IB and (optionally) group IIIA metals. The molten mixture may be coated onto a substrate in the molten state, e.g., using coating techniques such as hot-dipping, hot microgravure and/or air-knife coating. After coating, the substrate may be cooled and the film annealed, e.g., in a sulfur-containing or selenium-containing atmosphere.

Abstract: Photovoltaic devices, such as solar cells, and methods for their manufacture are disclosed. A device may be characterized by an architecture where two more materials having different electron affinities are regularly arrayed such that their presence alternates within distances of between about 1 nm and about 100 nm. The materials are present in a matrix based on a porous template with an array of template pores. The porous template is formed by anodizing a layer of metal. A photovoltaic device may include such a porous template disposed between a base electrode and a transparent conducting electrode. A first charge-transfer material fills the template pores, A second (complementary) charge-transfer material fills additional space not occupied by the first charge-transfer material.

Abstract: Photovoltaic devices, such as solar cells, and methods for their manufacture are disclosed. A device may be characterized by an architecture having a nanostructured template made from an n-type first charge transfer material with template elements between about 1 nm and about 500 nm in diameter with about 1012 to 1016 elements/m2. A p-type second charge-transfer material optionally coats the walls of the template elements leaving behind additional space. A p-type third charge-transfer material fills the additional space volumetrically interdigitating with the second charge transfer material.