Patents by Inventor Martin SCHLAEFFER

Martin SCHLAEFFER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12010215
    Abstract: Determining hash values based on at least two types of hash functions, utilizing a memory that is arranged to store at least one state to be used to determine hash values pursuant to a SHA-3 function, wherein hash values pursuant to any of a SHA-2 function or a SHA-1 function are determined based on the state.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: June 11, 2024
    Assignee: Infineon Technologies AG
    Inventor: Martin Schlaeffer
  • Patent number: 11907581
    Abstract: A data storage device comprises a plurality of storage elements, each storage element configured for storing a piece of information. The plurality of storage elements is accessible as a plurality of word sets, each word set comprising a set of storage elements, and is accessible as a plurality of slice sets, each slice set comprising a set of storage elements. Each storage element is a part of a word set and a part of a slice set. The device further comprises a control unit configured for obtaining word information and slice information and for executing a write operation to parallelly write the word information into a first word set of the plurality of word sets and the slice information into a first slice set of the plurality of slice sets, wherein the first word set and the first slice set comprise a common storage element defined by an overlap of the first word set and the first slice set in a layout of the plurality of storage elements.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: February 20, 2024
    Assignee: Infineon Technologies AG
    Inventors: Martin Schlaeffer, Osama Amin, Elif Bilge Kavun
  • Publication number: 20230370092
    Abstract: Error correction is proposed in which a syndrome calculation is carried out in a code domain of a second code and an efficient error correction algorithm is carried out in a code domain of a first code.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 16, 2023
    Inventors: Rainer Göttfert, Wieland Fischer, Berndt Gammel, Martin Schläffer
  • Publication number: 20230370091
    Abstract: Error correction is proposed, wherein, on the basis of a data word, a syndrome calculation is carried out with a matrix M on the basis of a matrix H of a code, and, if the result of the syndrome calculation reveals that the data word is erroneous, the result of the syndrome calculation is transformed by means of a linear mapping. Next, an error vector is determined on the basis of the result of the linear mapping by means of an efficient error correction algorithm and the erroneous data word is corrected on the basis of the error vector.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 16, 2023
    Inventors: Rainer Göttfert, Wieland Fischer, Berndt Gammel, Martin Schläffer
  • Patent number: 11755321
    Abstract: A circuit includes a data input that is configured to receive a data word, the data word including at least one operand which is rotated by a number of bits given by a rotation parameter, a first control input that is configured to receive the rotation parameter, a second control input that is configured to receive an indication of an operation to be performed, a first subcircuit that is configured to generate an operation- and rotation-dependent bit mask from the rotation parameter and the indication of the operation to be performed, a second subcircuit which is configured to process the at least one operand as a function of the bit mask and the operation to be performed, wherein the operand and the operation result generated by the processing remain in the rotated state, and a data output which is configured to output the operation result.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: September 12, 2023
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Florian Mendel, Martin Schlaeffer, Erich Wenger
  • Publication number: 20220291870
    Abstract: A data storage device comprises a plurality of storage elements, each storage element configured for storing a piece of information. The plurality of storage elements is accessible as a plurality of word sets, each word set comprising a set of storage elements, and is accessible as a plurality of slice sets, each slice set comprising a set of storage elements. Each storage element is a part of a word set and a part of a slice set. The device further comprises a control unit configured for obtaining word information and slice information and for executing a write operation to parallelly write the word information into a first word set of the plurality of word sets and the slice information into a first slice set of the plurality of slice sets, wherein the first word set and the first slice set comprise a common storage element defined by an overlap of the first word set and the first slice set in a layout of the plurality of storage elements.
    Type: Application
    Filed: March 8, 2022
    Publication date: September 15, 2022
    Inventors: Martin SCHLAEFFER, Osama AMIN, Elif Bilge KAVUN
  • Publication number: 20220278824
    Abstract: Determining hash values based on at least two types of hash functions, utilizing a memory that is arranged to store at least one state to be used to determine hash values pursuant to a SHA-3 function, wherein hash values pursuant to any of a SHA-2 function or a SHA-1 function are determined based on the state.
    Type: Application
    Filed: February 17, 2022
    Publication date: September 1, 2022
    Inventor: Martin Schlaeffer
  • Publication number: 20220237304
    Abstract: According to various embodiments, a data processing device is described comprising a memory configured to store data words in the form of at least two respective shares, a logic circuit configured to receive the at least two shares of at least one of the data words and to process the shares to generate at least two shares of a result data word, a remasking circuit configured to receive at least two shares of at least one of the data words and refresh the shares and an output circuit configured to store the at least two shares of the result data word or to store the refreshed at least two shares depending on a control sequence specifying a sequence of real operations and dummy operations.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 28, 2022
    Inventors: Martin Schlaeffer, Osama Amin, Elif Bilge Kavun
  • Publication number: 20220222076
    Abstract: A circuit includes a data input that is configured to receive a data word, the data word including at least one operand which is rotated by a number of bits given by a rotation parameter, a first control input that is configured to receive the rotation parameter, a second control input that is configured to receive an indication of an operation to be performed, a first subcircuit that is configured to generate an operation- and rotation-dependent bit mask from the rotation parameter and the indication of the operation to be performed, a second subcircuit which is configured to process the at least one operand as a function of the bit mask and the operation to be performed, wherein the operand and the operation result generated by the processing remain in the rotated state, and a data output which is configured to output the operation result.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 14, 2022
    Inventors: Florian MENDEL, Martin SCHLAEFFER, Erich WENGER