Abstract: In the described embodiments, entities in a computing device selectively write specified values to a lock variable in a local cache and one or more lower levels of a memory hierarchy to enable multiple entities to enable the concurrent execution of corresponding critical sections of program code that are protected by a same lock.

Abstract: A processing core of a plurality of processing cores is configured to execute a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for an issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.

Abstract: The described embodiments include a processor that handles operations during transactions. In these embodiments, the processor comprises one or more cores. During operation, at least one core is configured to monitor the acquisition of time stamps during transactions. The at least one core is further configured to prevent the acquisition of time stamps that meet predetermined conditions.

Abstract: In the described embodiments, entities in a computing device selectively write specified values to a lock variable in a local cache and one or more lower levels of a memory hierarchy to enable multiple entities to enable the concurrent execution of corresponding critical sections of program code that are protected by a same lock.

Abstract: A method and apparatus for compiling software written to be executed on a microprocessor that supports at least one hardware transactional memory function is provided. A compiler that supports at least one software transactional memory function is adapted to include a runtime system that maps between the at least one software transactional memory function and the at least one hardware transactional memory instruction.

Abstract: The described embodiments include a computing device that handles cache blocks during a transaction. In the described embodiments, after an entity has written to a cache block in a cache during the transaction, the computing device responds to a read request for the cache block from another entity with a copy of the cache block in a pre-transactional state. In these embodiments, the entity executing the transaction continues the transaction after the computing device responds to the read request from the other entity.

Abstract: A system and method for providing very large read-sets for hardware transactional memory with limited hardware support by monitoring meta data such as page table entries. The system and method include a Hardware-based Transactional Memory (HTM) mechanism that tracks meta-data such as page-table entries (PTE) rather than all the data itself. The HTM mechanism protects large regions of memory by providing conflict detection so that regions of memory can be located within a local read or write set.

Abstract: A system and method are disclosed for increasing large region transaction throughput by making informed determinations whether to abort a thread from a first core or a thread from a second core when a conflict is detected between the threads. Such a system and method allow resolution of conflicts between a first thread and a second thread. In certain embodiments, the system and method allow a requester to detect a conflict under specific circumstances and make an intelligent decision whether to abort the first thread, enter a wait state to give the first thread an opportunity to complete execution or, if possible, abort the second thread.

Abstract: A system and method are disclosed for increasing large region transaction throughput by making informed determinations whether to abort a thread from a first core or a thread from a second core when a conflict is detected between the threads. Such a system and method allow resolution of conflicts between a first thread and a second thread. In certain embodiments, the system and method allow a requester to detect a conflict under specific circumstances and make an intelligent decision whether to abort the first thread, enter a wait state to give the first thread an opportunity to complete execution or, if possible, abort the second thread.

Abstract: A system and method for providing very large read-sets for hardware transactional memory with limited hardware support by monitoring meta data such as page table entries. The system and method include a Hardware-based Transactional Memory (HTM) mechanism that tracks meta-data such as page-table entries (PTE) rather than all the data itself. The HTM mechanism protects large regions of memory by providing conflict detection so that regions of memory can be located within a local read or write set.

Abstract: A system and method are disclosed for allowing protection of larger areas than memory lines by monitoring accessed and dirty bits in page tables. More specifically, in some embodiments, a second associative structure with a different granularity is provided to filter out a large percentage of false positives. By providing the associative structure with sufficient size, the structure exactly specifies a region in which conflicting cache lines lie. If entries within this region are evicted from the structure, enabling the tracking for the entire index filters out a substantial number of false positives (depending on a granularity and a number of indices present). In some embodiments, this associative structure is similar to a translation look aside buffer (TLB) with 4 k, 2M entries.

Abstract: The described embodiments include a processor that handles operations during transactions. In these embodiments, the processor comprises one or more cores. During operation, at least one core is configured to monitor the acquisition of time stamps during transactions. The at least one core is further configured to prevent the acquisition of time stamps that meet predetermined conditions.

Abstract: A method is provided that includes determining a number of outstanding out-of-order instructions in an instruction stream. The method includes determining a number of available hardware resources for executing out-of-order instructions and inserting fencing instructions into the instruction stream if the number of outstanding out-of-order instructions exceeds the determined number of available hardware resources. A second method is provided for compiling source code that includes determining a speculative region. The second method includes generating machine-level instructions and inserting fencing instructions into the machine-level instructions in response to determining the speculative region. A processing device is provided that includes cache memory and a processing unit to execute processing device instructions in an instruction stream.

Abstract: In at least one embodiment, a method includes determining whether to elide a lock operation based on success of or failure of one or more previous transactional memory operations associated with one or more respective previous lock elisions. In at least one embodiment of the method, the lock operation is associated with a first access of a shared resource and the one or more previous lock elisions are associated with respective one or more previous accesses of the shared resource.

Abstract: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.

Abstract: A system and method are disclosed for allowing protection of larger areas than memory lines by monitoring accessed and dirty bits in page tables. More specifically, in some embodiments, a second associative structure with a different granularity is provided to filter out a large percentage of false positives. By providing the associative structure with sufficient size, the structure exactly specifies a region in which conflicting cache lines lie. If entries within this region are evicted from the structure, enabling the tracking for the entire index filters out a substantial number of false positives (depending on a granularity and a number of indices present). In some embodiments, this associative structure is similar to a translation look aside buffer (TLB) with 4 k, 2M entries.

Abstract: A method is provided for identifying a first portion of a computer program for speculative execution by a first processor element. At least one memory object is declared as being protected during the speculative execution. Thereafter, if a first signal is received indicating that the at least one protected memory object is to be accessed by a second processor element, then delivery of the first signal is delayed for a preselected duration of time to potentially allow the speculative execution to complete. The speculative execution of the first portion of the computer program may be aborted in response to receiving the delayed first signal before the speculative execution of the first portion of the computer program has been completed.

Abstract: A method and apparatus for compiling software written to be executed on a microprocessor that supports at least one hardware transactional memory function is provided. A compiler that supports at least one software transactional memory function is adapted to include a runtime system that maps between the at least one software transactional memory function and the at least one hardware transactional memory instruction.

Abstract: A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction.

Abstract: A processing core of a plurality of processing cores is configured to execute a speculative region of code as a single atomic memory transaction with respect one or more others of the plurality of processing cores. In response to determining an abort condition for an issued one of the plurality of program instructions and in response to determining that the issued program instruction is not part of a mispredicted execution path, the processing core is configured to abort an attempt to execute the speculative region of code.