Abstract: A system comprises data processing hardware and memory hardware. The memory hardware is in communication with the data processing hardware, and stores instructions that, when executed on the data processing hardware, cause the data processing hardware to perform a plurality of operations. In some examples, one of the operations may include receiving instance management configuration data for a single-tenant software-as-a-service (SaaS) application. Another operation may include further include receiving an image of the single-tenant SaaS application. Yet another operation can include generating, by the control plane manager, a control plane based on the instance management configuration data. The control plane is configured to create multiple instances of the single-tenant SaaS application based on the received image, and to manage the instances of the single-tenant SaaS application based on the received instance management configuration data.

Abstract: A system comprises data processing hardware and memory hardware. The memory hardware is in communication with the data processing hardware, and stores instructions that, when executed on the data processing hardware, cause the data processing hardware to perform a plurality of operations. In some examples, one of the operations may include receiving instance management configuration data for a single-tenant software-as-a-service (SaaS) application. Another operation may include further include receiving an image of the single-tenant SaaS application. Yet another operation can include generating, by the control plane manager, a control plane based on the instance management configuration data. The control plane is configured to create multiple instances of the single-tenant SaaS application based on the received image, and to manage the instances of the single-tenant SaaS application based on the received instance management configuration data.

Abstract: A system comprises data processing hardware and memory hardware. The memory hardware is in communication with the data processing hardware, and stores instructions that, when executed on the data processing hardware, cause the data processing hardware to perform a plurality of operations. In some examples, one of the operations may include receiving instance management configuration data for a single-tenant software-as-a-service (SaaS) application. Another operation may include further include receiving an image of the single-tenant SaaS application. Yet another operation can include generating, by the control plane manager, a control plane based on the instance management configuration data. The control plane is configured to create multiple instances of the single-tenant SaaS application based on the received image, and to manage the instances of the single-tenant SaaS application based on the received instance management configuration data.

Abstract: A system comprises data processing hardware and memory hardware. The memory hardware is in communication with the data processing hardware, and stores instructions that, when executed on the data processing hardware, cause the data processing hardware to perform a plurality of operations. In some examples, one of the operations may include receiving instance management configuration data for a single-tenant software-as-a-service (SaaS) application. Another operation may include further include receiving an image of the single-tenant SaaS application. Yet another operation can include generating, by the control plane manager, a control plane based on the instance management configuration data. The control plane is configured to create multiple instances of the single-tenant SaaS application based on the received image, and to manage the instances of the single-tenant SaaS application based on the received instance management configuration data.

Abstract: A system comprises data processing hardware and memory hardware. The memory hardware is in communication with the data processing hardware, and stores instructions that, when executed on the data processing hardware, cause the data processing hardware to perform a plurality of operations. In some examples, one of the operations may include receiving instance management configuration data for a single-tenant software-as-a-service (SaaS) application. Another operation may include further include receiving an image of the single-tenant SaaS application. Yet another operation can include generating, by the control plane manager, a control plane based on the instance management configuration data. The control plane is configured to create multiple instances of the single-tenant SaaS application based on the received image, and to manage the instances of the single-tenant SaaS application based on the received instance management configuration data.

Abstract: A system comprises data processing hardware and memory hardware. The memory hardware is in communication with the data processing hardware, and stores instructions that, when executed on the data processing hardware, cause the data processing hardware to perform a plurality of operations. In some examples, one of the operations may include receiving instance management configuration data for a single-tenant software-as-a-service (SaaS) application. Another operation may include further include receiving an image of the single-tenant SaaS application. Yet another operation can include generating, by the control plane manager, a control plane based on the instance management configuration data. The control plane is configured to create multiple instances of the single-tenant SaaS application based on the received image, and to manage the instances of the single-tenant SaaS application based on the received instance management configuration data.

Abstract: Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction.

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

Abstract: Enforcing limitations on hardware drivers. The method includes from a system kernel, assigning I/O resources to the system's root bus. From the root bus, the method further includes assigning a subset of the I/O resources to a device bus. Assigning a subset of the I/O resources to a device bus includes limiting the device bus to only be able to assign I/O resources that are assigned to it by the root bus. From the device bus, the method includes assigning I/O resources to a device through a device interface.

Abstract: A front-end compiler compiles source code into intermediate code, that may later be compiled into binary code. The source code defines an execution scope and includes a contract. When a contract is encountered at runtime of an execution scope, further execution of that execution scope is conditioned on whether a predicate associated with the contract is true. The front-end compiler operates so as to preserve the contract so that the contract continues to be semantically structured such that the predicate may be removed from the intermediate language code. The contract may thus continue to be understood by semantic analysis of the contract. Thus, the predicate may be understood by static analysis tools that operate on the intermediate code.

Abstract: The environment and use of an immutable buffer. A computing entity acquires data or generates data and populates the data into the buffer, after which the buffer is classified as immutable. The classification protects the data populated within the immutable buffer from changing during the lifetime of the immutable buffer, and also protects the immutable buffer from having its physical address changed during the lifetime of the immutable buffer. As different computing entities consume data from the immutable buffer, they do so through views provided by a view providing entity. The immutable buffer architecture may also be used for streaming data in which each component of the streaming data uses an immutable buffer. Accordingly, different computing entities may view the immutable data differently without having to actually copy the data.

Abstract: Monitoring performance of one or more architecturally significant processor caches coupled to a processor. The methods include executing an application on one or more processors coupled to one or more architecturally significant processor caches, where the application utilizes the architecturally significant portions of the architecturally significant processor caches. The methods further include at least one of generating metrics related to performance of the architecturally significant processor caches; implementing one or more debug exceptions related to performance of the architecturally significant processor caches; or implementing one or more transactional breakpoints related to performance of the architecturally significant processor caches as a result of utilizing the architecturally significant portions of the architecturally significant processor caches.

Abstract: Type casting in a managed code system is described. The managed code system includes managed memory as well as shared memory located outside of the managed memory. The managed memory has multiple managed memory portions, each corresponding to a computing entity, such as a processes. The type system permits obtaining of data from shared memory using type casting to thereby assign the data a type that supports type casting. The type is a valid type casting type that satisfies certain requirements that allow the type to be assigned while maintaining type safety.

Abstract: Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter.

Abstract: A managed memory in which multiple computing entities each have a corresponding entity-specific portion that is subject to garbage collection. An immutable buffer is located outside of managed memory. For a given computing entity, the corresponding managed memory portion contains entity-specific objects that can be accessed by a specific computing entity, but not by the other multiple computing entities. For one or more of the entity-specific managed memory portions, the portion also includes a reference to shared memory, such as an immutable buffer. The reference is structured to be ignored by the garbage collector, though the reference may appear just as a normal object in the managed memory portion. Thus, a unified memory access model is made possible in which the methods for a computing entity to access a regular object in managed memory is similar to how the computing entity accesses shared memory.

Abstract: In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread. Other embodiments are described and claimed.

Abstract: A front-end compiler compiles source code into intermediate code, that may later be compiled into binary code. The source code defines an execution scope and includes a contract. When a contract is encountered at runtime of an execution scope, further execution of that execution scope is conditioned on whether a predicate associated with the contract is true. The front-end compiler operates so as to preserve the contract so that the contract continues to be semantically structured such that the predicate may be removed from the intermediate language code. The contract may thus continue to be understood by semantic analysis of the contract. Thus, the predicate may be understood by static analysis tools that operate on the intermediate code.

Abstract: Type casting in a managed code system is described. The managed code system includes managed memory as well as shared memory located outside of the managed memory. The managed memory has multiple managed memory portions, each corresponding to a computing entity, such as a processes. The type system permits obtaining of data from shared memory using type casting to thereby assign the data a type that supports type casting. The type is a valid type casting type that satisfies certain requirements that allow the type to be assigned while maintaining type safety.

Abstract: A managed memory in which multiple computing entities each have a corresponding entity-specific portion that is subject to garbage collection. An immutable buffer is located outside of managed memory. For a given computing entity, the corresponding managed memory portion contains entity-specific objects that can be accessed by a specific computing entity, but not by the other multiple computing entities. For one or more of the entity-specific managed memory portions, the portion also includes a reference to shared memory, such as an immutable buffer. The reference is structured to be ignored by the garbage collector, though the reference may appear just as a normal object in the managed memory portion. Thus, a unified memory access model is made possible in which the methods for a computing entity to access a regular object in managed memory is similar to how the computing entity accesses shared memory.