Abstract: A transparent coversheet intervenes between a lens and a thinned die in a visible light fault analysis tool so that the thinned die is robust to fractures. In addition, the transparent coversheet has a greater thermal mass than the thinned die and thus acts as a heat sink to prevent active circuitry in the thinned die from overheating during the visible light fault analysis.

Abstract: A transparent coversheet intervenes between a lens and a thinned die in a visible light fault analysis tool so that the thinned die is robust to fractures. In addition, the transparent coversheet has a greater thermal mass than the thinned die and thus acts as a heat sink to prevent active circuitry in the thinned die from overheating during the visible light fault analysis.

Abstract: A method and apparatus for mapping an electronic device. The electronic device is loaded into a test fixture, which may be an automated test equipment (ATE). A laser beam is stepped across locations of interest. At each location of interest a minimum voltage and/or maximum frequency are computed. A contour map of the changes in minimum voltage and maximum frequency across a field of view of the electronic device is generated. Additional embodiments provide signaling a laser scan module during the rising edge of a synchronization pulse to indicate that minimum voltage (Vmin) and maximum frequency (Fmax) specification search data is provided to a laser voltage probe. A Vmin/Fmax module compares the specification search data with the data read from the laser voltage probe and computes a parameter shift value. The laser beam is moved to another location when the falling edge of the synchronization pulse occurs.

Abstract: A method and apparatus for mapping an electronic device. The electronic device is loaded into a test fixture, which may be an automated test equipment (ATE). A laser beam is stepped across locations of interest. At each location of interest a minimum voltage and/or maximum frequency are computed. A contour map of the changes in minimum voltage and maximum frequency across a field of view of the electronic device is generated. Additional embodiments provide signaling a laser scan module during the rising edge of a synchronization pulse to indicate that minimum voltage (Vmin) and maximum frequency (Fmax) specification search data is provided to a laser voltage probe. A Vmin/Fmax module compares the specification search data with the data read from the laser voltage probe and computes a parameter shift value. The laser beam is moved to another location when the falling edge of the synchronization pulse occurs.

Abstract: A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure.

Abstract: A semiconductor die includes a group of spacer cells within the semiconductor die. The spacer cells include fiducial markings therein. The fiducial markings can be located within a metal layer, a diffusion layer, a polysilicon layer, and/or a Shallow Trench Isolation (STI) structure.

Abstract: Electronic devices, such as IC devices, are tested by determining a failure net within the electronic device that is causing a device failure. After identifying the failure net, the failure net is locally stressed. The stress is applied so that only the net being tested is subjected to the stress, and the remaining nets and components of the device are not stressed. A change in a signal produced by the failure net is observed while the failure net is being subjected to the stress. Testing in this manner assists in identifying the failure net as a failure source of the device.

Abstract: Electronic devices, such as IC devices, are tested by determining a failure net within the electronic device that is causing a device failure. After identifying the failure net, the failure net is locally stressed. The stress is applied so that only the net being tested is subjected to the stress, and the remaining nets and components of the device are not stressed. A change in a signal produced by the failure net is observed while the failure net is being subjected to the stress. Testing in this manner assists in identifying the failure net as a failure source of the device.