Patents by Inventor Martin Zgaga
Martin Zgaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10672716Abstract: An integrated circuit substrate and a method for manufacturing the same are disclosed. In an embodiment a method includes providing a wafer having a plurality of active areas, each active area being provided in a separate die area and for each active area, providing a code pattern outside the active area, the code pattern being associated with the die area.Type: GrantFiled: July 9, 2018Date of Patent: June 2, 2020Assignee: Infineon Technologies AGInventors: Michael Roesner, Gudrun Stranzl, Manfred Engelhardt, Martin Zgaga
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Patent number: 10157765Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.Type: GrantFiled: November 23, 2016Date of Patent: December 18, 2018Assignee: Infineon Technologies AGInventors: Gudrun Stranzl, Martin Zgaga, Rainer Leuschner, Bernhard Goller, Bernhard Boche, Manfred Engelhardt, Hermann Wendt, Bernd Noehammer, Karl Mayer, Michael Roesner, Monika Cornelia Voerckel
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Publication number: 20180315713Abstract: An integrated circuit substrate and a method for manufacturing the same are disclosed. In an embodiment a method includes providing a wafer having a plurality of active areas, each active area being provided in a separate die area and for each active area, providing a code pattern outside the active area, the code pattern being associated with the die area.Type: ApplicationFiled: July 9, 2018Publication date: November 1, 2018Inventors: Michael Roesner, Gudrun Stranzl, Manfred Engelhardt, Martin Zgaga
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Patent number: 10020264Abstract: The description discloses a method for use in manufacturing integrated circuit chips. The method comprises providing a wafer having a plurality of integrated circuits each provided in an separate active areas, and, for each active area, outside the active area, providing a code pattern that is associated with the integrated circuit. A computer-readable medium is also disclosed. Further, a manufacturing apparatus configured to receive a wafer and to remove material from the wafer so as to provide a scribe line to the wafer formed as a trench for use in separation of the wafer into dies is also disclosed. The description also discloses a wafer, an integrated circuit chip die substrate originating from a wafer of origin and carrying an integrated circuit, and an integrated circuit chip.Type: GrantFiled: April 28, 2015Date of Patent: July 10, 2018Assignee: Infineon Technologies AGInventors: Michael Roesner, Gudrun Stranzl, Manfred Engelhardt, Martin Zgaga
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Patent number: 10005659Abstract: A hole plate and a MEMS microphone arrangement are disclosed. In an embodiment a hole plate includes a substrate with a first main surface, a second main surface, and a lateral surface and a perforation structure formed within the substrate, the perforation structure having a plurality of through-holes through the substrate, wherein the through-holes and the lateral surface are a result of a simultaneous dry etching step.Type: GrantFiled: February 23, 2017Date of Patent: June 26, 2018Assignee: Infineon Technologies AGInventors: Thomas Grille, Ursula Hedenig, Michael Roesner, Gudrun Stranzl, Martin Zgaga
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Patent number: 9741618Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.Type: GrantFiled: December 22, 2015Date of Patent: August 22, 2017Assignee: Infineon Technologies AGInventors: Gudrun Stranzl, Martin Zgaga, Markus Kahn, Guenter Denifl
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Patent number: 9708182Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.Type: GrantFiled: August 28, 2015Date of Patent: July 18, 2017Assignee: Infineon Technologies AGInventors: Andreas Behrendt, Kai-Alexander Schreiber, Sokratis Sgouridis, Martin Zgaga, Bernhard Winkler
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Publication number: 20170194205Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.Type: ApplicationFiled: December 22, 2015Publication date: July 6, 2017Inventors: Gudrun Stranzl, Martin Zgaga, Markus Kahn, Guenter Denifl
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Publication number: 20170158493Abstract: A hole plate and a MEMS microphone arrangement are disclosed. In an embodiment a hole plate includes a substrate with a first main surface, a second main surface, and a lateral surface and a perforation structure formed within the substrate, the perforation structure having a plurality of through-holes through the substrate, wherein the through-holes and the lateral surface are a result of a simultaneous dry etching step.Type: ApplicationFiled: February 23, 2017Publication date: June 8, 2017Inventors: Thomas Grille, Ursula Hedenig, Michael Roesner, Gudrun Stranzl, Martin Zgaga
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Patent number: 9673096Abstract: According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.Type: GrantFiled: November 14, 2014Date of Patent: June 6, 2017Assignees: INFINEON TECHNOLOGIES AG, Technische Universitaet GrazInventors: Joachim Hirschler, Michael Roesner, Markus Juch Heinrici, Gudrun Stranzl, Martin Mischitz, Martin Zgaga
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Patent number: 9610543Abstract: A method for structuring a substrate and a structured substrate are disclosed. In an embodiment a method includes providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface, performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.Type: GrantFiled: January 31, 2014Date of Patent: April 4, 2017Assignee: Infineon Technologies AGInventors: Thomas Grille, Ursula Hedenig, Michael Roesner, Gudrun Stranzl, Martin Zgaga
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Publication number: 20170076970Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.Type: ApplicationFiled: November 23, 2016Publication date: March 16, 2017Inventors: Gudrun Stranzl, Martin Zgaga, Rainer Leuschner, Bernhard Goller, Bernhard Boche, Manfred Engelhardt, Hermann Wendt, Bernd Noehammer, Karl Mayer, Michael Roesner, Monika Cornelia Voerckel
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Patent number: 9496193Abstract: A semiconductor chip includes a body having a frontside, a backside opposite the frontside, and sidewalls extending between the backside and frontside, at least a portion of each sidewall having a defined surface structure with hydrophobic characteristics to inhibit travel of a bonding material along the sidewalls during attachment of the semiconductor chip to a carrier with the bonding material.Type: GrantFiled: September 18, 2015Date of Patent: November 15, 2016Assignee: Infineon Technologies AGInventors: Michael Roesner, Gudrun Stranzl, Martin Zgaga, Martin Sporn, Tobias Schmidt
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Publication number: 20160322306Abstract: The description discloses a method for use in manufacturing integrated circuit chips. The method comprises providing a wafer having a plurality of integrated circuits each provided in an separate active areas, and, for each active area, outside the active area, providing a code pattern that is associated with the integrated circuit. A computer-readable medium is also disclosed. Further, a manufacturing apparatus configured to receive a wafer and to remove material from the wafer so as to provide a scribe line to the wafer formed as a trench for use in separation of the wafer into dies is also disclosed. The description also discloses a wafer, an integrated circuit chip die substrate originating from a wafer of origin and carrying an integrated circuit, and an integrated circuit chip.Type: ApplicationFiled: April 28, 2015Publication date: November 3, 2016Inventors: Michael Roesner, Gudrun Stranzl, Manfred Engelhardt, Martin Zgaga
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Patent number: 9481563Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a micro-mechanical structure and a semiconductor material arranged over the micro-mechanical structure. A side surface of the semiconductor material includes a first region and a second region. The first region has an undulation, and the second region is a peripheral region of the side surface and decreases towards the micro-mechanical structure.Type: GrantFiled: March 11, 2015Date of Patent: November 1, 2016Assignee: Infineon Technologies AGInventors: Manfred Engelhardt, Martin Zgaga
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Patent number: 9257342Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.Type: GrantFiled: April 24, 2014Date of Patent: February 9, 2016Assignee: Infineon Technologies AGInventors: Gudrun Stranzl, Martin Zgaga, Markus Kahn, Guenter Denifl
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Publication number: 20150368097Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.Type: ApplicationFiled: August 28, 2015Publication date: December 24, 2015Inventors: Andreas Behrendt, Kai-Alexander Schreiber, Sokratis Sgouridis, Martin Zgaga, Bernhard Winkler
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Patent number: 9139427Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.Type: GrantFiled: April 17, 2013Date of Patent: September 22, 2015Assignee: Infineon Technologies AGInventors: Andreas Behrendt, Kai-Alexander Schreiber, Sokratis Sgouridis, Martin Zgaga, Bernhard Winkler
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Publication number: 20150217997Abstract: A method for structuring a substrate and a structured substrate are disclosed. In an embodiment a method includes providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface, performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.Type: ApplicationFiled: January 31, 2014Publication date: August 6, 2015Inventors: Thomas Grille, Ursula Hedenig, Michael Roesner, Gudrun Stranzl, Martin Zgaga
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Publication number: 20150183631Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a micro-mechanical structure and a semiconductor material arranged over the micro-mechanical structure. A side surface of the semiconductor material includes a first region and a second region. The first region has an undulation, and the second region is a peripheral region of the side surface and decreases towards the micro-mechanical structure.Type: ApplicationFiled: March 11, 2015Publication date: July 2, 2015Inventors: Manfred Engelhardt, Martin Zgaga