Patents by Inventor Martina Hommel

Martina Hommel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9543199
    Abstract: An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: January 10, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Oliver Aubel, Wolfgang Hasse, Martina Hommel, Heinrich Koerner
  • Patent number: 9269669
    Abstract: A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: February 23, 2016
    Assignee: Infineon Technologies AG
    Inventors: Johann Helneder, Markus Schwerd, Thomas Goebel, Andrea Mitchell, Heinrich Koerner, Martina Hommel
  • Publication number: 20160049329
    Abstract: An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.
    Type: Application
    Filed: December 23, 2013
    Publication date: February 18, 2016
    Inventors: Oliver Aubel, Wolfgang Hasse, Martina Hommel, Heinrich Koerner
  • Patent number: 8643183
    Abstract: An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: February 4, 2014
    Assignee: Infineon Technologies AG
    Inventors: Oliver Aubel, Wolfgang Hasse, Martina Hommel, Heinrich Koerner
  • Patent number: 8258628
    Abstract: An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: September 4, 2012
    Assignee: Infineon Technologies AG
    Inventors: Martina Hommel, Heinrich Koerner, Markus Schwerd, Martin Seck
  • Publication number: 20120149168
    Abstract: A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.
    Type: Application
    Filed: February 23, 2012
    Publication date: June 14, 2012
    Inventors: Johann Helneder, Markus Schwerd, Thomas Goebel, Andrea Mitchell, Heinrich Koerner, Martina Hommel
  • Patent number: 7964494
    Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: June 21, 2011
    Assignee: Infineon Technologies AG
    Inventors: Stefan Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck
  • Patent number: 7667256
    Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structure levels in which in each case elongated interconnects are arranged.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: February 23, 2010
    Assignee: Infineon Technologies AG
    Inventors: Martina Hommel, Heinrich Koerner, Markus Schwerd, Martin Seck
  • Patent number: 7656037
    Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structures levels and elongated interconnects.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: February 2, 2010
    Assignee: Infineon Technologies AG
    Inventors: Martina Hommel, Heinrich Koerner, Markus Schwerd, Martin Seck
  • Publication number: 20100007027
    Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.
    Type: Application
    Filed: September 18, 2009
    Publication date: January 14, 2010
    Inventors: Stephen Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Körner, Andrea Mitchell, Markus Schwerd, Martin Seck
  • Patent number: 7619309
    Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: November 17, 2009
    Assignee: Infineon Technologies AG
    Inventors: Stefan Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Kôrner, Andrea Mitchell, Markus Schwerd, Martin Seck
  • Publication number: 20080224318
    Abstract: An integrated circuit arrangement includes a substrate with a multiplicity of integrated semiconductor components arranged therein, the substrate having a wiring interconnect near to the substrate, a middle wiring interconnect and a wiring interconnect remote from the substrate, which are arranged in this order at increasing distance from the substrate.
    Type: Application
    Filed: September 20, 2006
    Publication date: September 18, 2008
    Inventors: Martina Hommel, Heinrich Koerner, Markus Schwerd, Martin Seck
  • Publication number: 20070105366
    Abstract: An explanation is given of, inter alia, methods in which the barrier material is removed at a via bottom or at a via top area by long-term heat treatment. Concurrently or alternatively, interconnects are coated with barrier material in a simple and uncomplicated manner by means of the long-term heat treatment.
    Type: Application
    Filed: October 30, 2006
    Publication date: May 10, 2007
    Inventors: Oliver Aubel, Wolfgang Hasse, Martina Hommel, Heinrich Koerner
  • Publication number: 20070071052
    Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structure levels in which in each case elongated interconnects are arranged.
    Type: Application
    Filed: September 21, 2006
    Publication date: March 29, 2007
    Inventors: Martina Hommel, Heinrich Koerner, Markus Schwerd, Martin Seck
  • Publication number: 20070071053
    Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes at least three conductive structures levels and elongated interconnects.
    Type: Application
    Filed: September 21, 2006
    Publication date: March 29, 2007
    Inventors: Martina Hommel, Heinrich Koerner, Markus Schwerd, Martin Seck
  • Publication number: 20060222760
    Abstract: A multifunctional dielectric layer can be formed on a substrate, especially on an exposed metallic strip conductor system on a substrate. An additional metal layer is formed across the surface of the exposed metal strip conductors. The metal layer is then at least partially converted to a nonconducting metal oxide, the dielectric layer.
    Type: Application
    Filed: March 21, 2006
    Publication date: October 5, 2006
    Inventors: Johann Helneder, Markus Schwerd, Thomas Goebel, Andrea Mitchell, Heinrich Koerner, Martina Hommel
  • Publication number: 20060192289
    Abstract: A connection arrangement having an outer conductive structure arranged at least partly or completely in a cutout of an electrical insulation layer is provided. An inner conductive structure is arranged at the bottom of the cutout on one side of the insulation layer. The inner conductive structure adjoins the outer conductive structure in a contact zone. A contact area is arranged at the outer conductive structure on the other side of the cutout. The contact zone and the contact area do not overlap. The bottom of the cutout is arranged to overlaps at least half of the contact area, to provide a step in the insulation layer at the edge of the cutout outside a main current path between the contact area and the inner conductive structure.
    Type: Application
    Filed: February 9, 2006
    Publication date: August 31, 2006
    Inventors: Stefan Drexl, Thomas Goebel, Johann Helneder, Martina Hommel, Wolfgang Klein, Heinrich Korner, Andrea Mitchell, Markus Schwerd, Martin Seck