Abstract: The configurable logic device comprises a plurality of configurable logic cells (2). A configurable logic cell comprises a plurality of multi-bit registers (20a, 20b, 20c, 20d). At least one is accessible both in a parallel and in a serial fashion. A functional unit (30) therein is coupled to two or more of the registers and comprises a chain of functional unit segments (31, 31?) that each comprise an AND gate (33) and a 1-bit full adder (32) receiving an output of the AND-gate. An output selection facility (50) provides an output signal of the configurable logic cell selected from two or more input signals. At least one of the input signals is provided by one of the multi-bit registers, and another by the functional unit.

Abstract: The configurable logic device comprises a plurality of configurable logic cells (2). A configurable logic cell comprises a plurality of multi-bit registers (20a, 20b, 20c, 20d). At least one is accessible both in a parallel and in a serial fashion. A functional unit (30) therein is coupled to two or more of the registers and comprises a chain of functional unit segments (31, 31?) that each comprise an AND gate (33) and a 1-bit full adder (32) receiving an output of the AND-gate. An output selection facility (50) provides an output signal of the configurable logic cell selected from two or more input signals. At least one of the input signals is provided by one of the multi-bit registers, and another by the functional unit.

Abstract: The configurable logic device comprises a plurality of configurable logic cells (2). A configurable logic cell comprises a plurality of multi-bit registers (20a, 20b, 20c, 2Od). At least one is accessible both in a parallel and in a serial fashion. A functional unit (30) therein is coupled to two or more of the registers and comprises a chain of functional unit segments (31, 31?) that each comprise an AND gate (33) and a 1-bit full adder (32) receiving an output of the AND-gate. An output selection facility (50) provides an output signal of the configurable logic cell selected from two or more input signals. At least one of the input signals is provided by one of the multi-bit registers, and another by the functional unit.

Abstract: The invention relates to a method of manufacturing openings in a substrate (5), the method comprising steps of: providing the substrate (5) with a masking layer (40) on a surface thereof; forming a first opening (10), a second opening (30), and a channel (20) in between the first opening (10) and the second opening (30) in the masking layer (40), the channel (20) connecting the first opening (10) with the second opening (30), the second opening (30) having an area (A2) that is larger than the area (A1) of the first opening (10); forming trenches (11, 21, 31) in the substrate (5) located at the first opening (10), the second opening (30), and at the channel (20) under masking of the masking layer (40) by means of anisotropic dry etching, and sealing off the trench (21) located at the channel (20) for forming the openings in the substrate (5). The method of the invention enables formation of a deeper first opening (10) than what is possible with the known methods.

Abstract: A circuit has a plurality of functional circuits (100a-f), each with multiphase control inputs. A control circuit drives the inputs for each phase in parallel. The control circuit (120a-c) comprises a chain of one-shot circuits (120a-c), each comprising a bi-stable circuit (121). The bi-stable circuit (121) of a first one-shot circuit in the chain has a set input coupled to the basic control signal input (126), the bi-stable circuits (121) of a remaining or each remaining one-shot circuit (120a-c) in the chain have a set input output of its predecessor in the chain. Each bi-stable circuit (121) has an output coupled to a respective one of the multiphase control outputs (14a-c) and a reset input coupled to the respective one of the multiphase control outputs (14a-c). Loading of the multiphase control outputs (14a-c) by the functional circuits results in a delay of the reset.

Abstract: An integrated circuit comprises a matrix (10) of programmable cells (100). Each particular one of the programmable cells (100) comprises a programmable logic circuit (22) and a bank (24) of routing multiplexers (25a-d). Each routing multiplexer (25a-d) in the bank (24) has a set of inputs connected to connections selected from a group consisting of connections to an output of the programmable logic circuit (22) and connections dedicated to outputs of routing multiplexers (25a-d) in further ones of the programmable cells (100) other than the particular one of the programmable cells (100). The further ones of the programmable cells (100) the inputs of the routing multiplexer (25a-d) in the bank (24) are connected to are positioned relative to the particular one of the programmable cells (100) in the matrix (10) in neighboring cells (100) of the particular one of the programmable cells (100) and in cells (100) beyond the neighboring cells (100).

Abstract: The configurable logic device comprises a plurality of configurable logic cells (2). A configurable logic cell comprises a plurality of multi-bit registers (20a, 20b, 20c, 20d). At least one is accessible both in a parallel and in a serial fashion. A functional unit (30) therein is coupled to two or more of the registers and comprises a chain of functional unit segments (31, 31?) that each comprise an AND gate (33) and a 1-bit full adder (32) receiving an output of the AND-gate. An output selection facility (50) provides an output signal of the configurable logic cell selected from two or more input signals. At least one of the input signals is provided by one of the multi-bit registers, and another by the functional unit.

Abstract: An integrated circuit comprises a matrix (10) of programmable cells (100). Each particular one of the programmable cells (100) comprises a programmable logic circuit (22) and a bank (24) of routing multiplexers (25a-d). Each routing multiplexer (25a-d) in the bank (24) has a set of inputs connected to connections selected from a group consisting of connections to an output of the programmable logic circuit (22) and connections dedicated to outputs of routing multiplexers (25a-d) in further ones of the programmable cells (100) other than the particular one of the programmable cells (100). The further ones of the programmable cells (100) the inputs of the routing multiplexer (25a-d) in the bank (24) are connected to are positioned relative to the particular one of the programmable cells (100) in the matrix (10) in neighboring cells (100) of the particular one of the programmable cells (100) and in cells (100) beyond the neighboring cells (100).

Abstract: The invention relates to a method of manufacturing openings in a substrate (5), the method comprising steps of: providing the substrate (5) with a masking layer (40) on a surface thereof; forming a first opening (10), a second opening (30), and a channel (20) in between the first opening (10) and the second opening (30) in the masking layer (40), the channel (20) connecting the first opening (10) with the second opening (30), the second opening (30) having an area (A2) that is larger than the area (A1) of the first opening (10); forming trenches (11, 21, 31) in the substrate (5) located at the first opening (10), the second opening (30), and at the channel (20) under masking of the masking layer (40) by means of anisotropic dry etching, and sealing off the trench (21) located at the channel (20) for forming the openings in the substrate (5). The method of the invention enables formation of a deeper first opening (10) than what is possible with the known methods.

Abstract: A circuit has a plurality of functional circuits (100a-f), each with multiphase control inputs. A control circuit drives the inputs for each phase in parallel. The control circuit (120a-c) comprises a chain of one-shot circuits (120a-c), each comprising a bi-stable circuit (121). The bi-stable circuit (121) of a first one-shot circuit in the chain has a set input coupled to the basic control signal input (126), the bi-stable circuits (121) of a remaining or each remaining one-shot circuit (120a-c) in the chain have a set input output of its predecessor in the chain. Each bi-stable circuit (121) has an output coupled to a respective one of the multiphase control outputs (14a-c) and a reset input coupled to the respective one of the multiphase control outputs (14a-c). Loading of the multiphase control outputs (14a-c) by the functional circuits results in a delay of the reset.