Abstract: Apparatus is disclosed for buffering writes from a CPU to main memory, in which sequential write requests to the same address are gathered and combined into a single write request. The embodiment described does not permit gathering with the write request in the buffer which is next scheduled for action by the main memory bus controller, nor does it permit gathering with other than the immediately preceding write request. The invention is implemented using a plurality of buffer ranks, each comprising a data rank, an address rank, and a valid rank for indicating which bits or bytes of the data rank contain data to be written to memory.

Abstract: A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.

Abstract: A data processor capable of automatically storing in an external memory all essential information relating to the internal state thereof upon the detection of an access fault during instruction execution. Upon correction of the cause of the fault, the data processor automatically retrieves the stored state information and restores the state thereof in accordance with the retrieved state information. The data processor then resumes execution of the instruction. The faulted access may be selectively rerun upon the resumption of instruction execution. Means are provided to verify that the retrieved state information is valid.