Patents by Inventor Marvin Gestole

Marvin Gestole has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090057855
    Abstract: A semiconductor die package. It includes a semiconductor die including a first surface and a second surface opposite the first surface, an optional conductive structure, and a leadframe structure. The leadframe structure comprises a central portion suitable for supporting the semiconductor die, and a plurality of stand-off structures coupled to the central portion of the leadframe structure. The stand-off structures can support the conductive structure, and the conductive structure is attached to the second surface of the semiconductor die.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 5, 2009
    Inventors: Maria Clemens Quinones, Erwin Victor Cruz, Marvin Gestole, Ruben P. Madrid, Connie N. Tangpuz
  • Patent number: 7402462
    Abstract: A folded frame carrier has a die attach pad (DAP) 30 and one or more folded edges 32, 33, 34, 35. Each folded edge has one or more studs 36 and each stud has a trapezoidal tip. The folded frame carrier may be made of single gauge copper or copper alloy. Multiple folded frame carriers may be formed between opposite rails of a lead frame. The folded edges are cut with a relief groove. The tips are formed in edges of the DAP and then the tips are folded upright. The tips provide electrical connection to the terminal on the rear surface of a power semiconductor mounted on the DAP.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: July 22, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ruben P. Madrid, Marvin Gestole, Erwin Victor R. Cruz, Romel N. Madatad, Arniel Jaud, Paul Armand Calo
  • Publication number: 20070015316
    Abstract: A folded frame carrier has a die attach pad (DAP) 30 and one or more folded edges 32, 33, 34, 35. Each folded edge has one or more studs 36 and each stud has a trapezoidal tip. The folded frame carrier may be made of single gauge copper or copper alloy. Multiple folded frame carriers may be formed between opposite rails of a lead frame. The folded edges are cut with a relief groove. The tips are formed in edges of the DAP and then the tips are folded upright. The tips provide electrical connection to the terminal on the rear surface of a power semiconductor mounted on the DAP.
    Type: Application
    Filed: July 12, 2005
    Publication date: January 18, 2007
    Inventors: Ruben Madrid, Marvin Gestole, Erwin R. Cruz, Romel Madatad, Arniel Jaud, Paul Calo
  • Publication number: 20060231933
    Abstract: A method for making a flip chip in a leaded molded package is disclosed. In some embodiments, the method includes using a leadframe structure including a die attach region and leads. The die attach region includes depressions proximate the inner portions of the leads, and an aperture in the die attach region. A semiconductor die is mounted to the die attach region. A molding material passes through the aperture and covers the first surface of the semiconductor die and the die attach region.
    Type: Application
    Filed: June 1, 2006
    Publication date: October 19, 2006
    Inventors: Elsie Cabahug, Marvin Gestole, Margie Tumulak-Rios, Lilith Montayre, Romel Manatad