Abstract: A computing system configured to optimize computing resources distribution includes a hardware platform which includes a physical instruction processor (IP); a kernel structure executed on the hardware platform which includes an emulated IP; an emulated operating system executed on the kernel structure; and a performance monitor executed on the emulated operating system. The performance monitor interrogates the emulated IP to obtain performance information which includes a time of executing an instruction at the kernel structure; a time of executing an instruction at an application software level; bytes received by the emulated IP through a networking interface; and bytes transmitted by the emulated IP through the networking interface.

Abstract: A cleaning system for use with a heat exchanger and a fluid pressurizing assembly includes a wand assembly, a pivot assembly, and a movement mechanism having a body and a piston rod moveable relative the body in response to fluid pressurization. The wand assembly includes a wand in fluid communication with the fluid pressurizing assembly, and having a first orifice configured to eject fluid toward the heat exchanger. The wand is supported by the pivot assembly such that the wand is selectively pivotable about a first pivot axis. The movement mechanism connects to the pivot assembly at a second pivot axis offset from the first pivot axis such that selective movement of the piston rod produces pivotal movement of the wand about the first pivot axis.

Abstract: A cleaning system for use with a heat exchanger and a fluid pressurizing assembly includes a wand assembly, a pivot assembly, and a movement mechanism having a body and a piston rod moveable relative the body in response to fluid pressurization. The wand assembly includes a wand in fluid communication with the fluid pressurizing assembly, and having a first orifice configured to eject fluid toward the heat exchanger. The wand is supported by the pivot assembly such that the wand is selectively pivotable about a first pivot axis. The movement mechanism connects to the pivot assembly at a second pivot axis offset from the first pivot axis such that selective movement of the piston rod produces pivotal movement of the wand about the first pivot axis.

Abstract: A cleaning system for use with a heat exchanger and a fluid pressurizing assembly includes a wand assembly, a pivot assembly, and a movement mechanism having a body and a piston rod moveable relative the body in response to fluid pressurization. The wand assembly includes a wand in fluid communication with the fluid pressurizing assembly, and having a first orifice configured to eject fluid toward the heat exchanger. The wand is supported by the pivot assembly such that the wand is selectively pivotable about a first pivot axis. The movement mechanism connects to the pivot assembly at a second pivot axis offset from the first pivot axis such that selective movement of the piston rod produces pivotal movement of the wand about the pivot axis.

Abstract: A cleaning system for use with a heat exchanger and a fluid pressurizing assembly includes a wand assembly, a pivot assembly, and a movement mechanism having a body and a piston rod moveable relative the body in response to fluid pressurization. The wand assembly includes a wand in fluid communication with the fluid pressurizing assembly, and having a first orifice configured to eject fluid toward the heat exchanger. The wand is supported by the pivot assembly such that the wand is selectively pivotable about a first pivot axis. The movement mechanism connects to the pivot assembly at a second pivot axis offset from the first pivot axis such that selective movement of the piston rod produces pivotal movement of the wand about the pivot axis.

Abstract: A method and computer storage medium useable for estimating expected processor utilization for a workload on a computing system are disclosed. One method includes calculating an estimated throughput for a first computing system using a predetermined model based on physical characteristics of the first computing system. The method further includes determining an estimated utilization of the first computing system based on a utilization of a second computing system and a ratio of throughput of the second computing system to the estimated throughput of the first computing system.

Abstract: An improved system and method for completing performance analysis for a target system is disclosed. According to the current invention, different types of configurations files are created, each to describe one or more respective aspects and/or portions of the target system. Each of these file types may include a combination of parameter values and equations that represent the respective portion of the system. After the configuration files are defined, scenarios are created. Each scenario includes a set of configuration files, with some or all of the files being of different file types. The files included within a scenario provide all parameter values and equations needed to calculate performance data for a particular revision of the target system. Next, a performance study is defined to include one or more of the scenarios. Finally, performance data is derived for each of the scenarios in the performance study.

Abstract: In particular, a system and method for receiving high speed processor bus traces for study of computer system capacity and operation uses a small FIFO memory and skips unused bus cycles to avoid the requirement for memory speed to match the processor bus speed. A time stamp is obtained to match each processor word to a time of occurrence to facilitate study of the trace data. Triggers are established to capture only those processor words that appear on the bus and which are also of interest. The remaining words are compacted by removing parts of the words that are not of interest from those words that remain in the queue based on the trigger criteria.

Abstract: Methods and systems are provided for efficiently predicting the instruction execution efficiency of a proposed computer system. This is accomplished by first measuring or otherwise obtaining actual instruction execution efficiency values for two or more actual computer systems. The actual instruction execution efficiency values are preferably measured using a sufficient number of actual computer systems that have a sufficient variety of resource allocations to create a statistically significant pool of information or data. Using this pool of information or data, a predicted instruction execution efficiency value is calculated for a proposed computer system having a proposed allocation of resources of the first resource type and the second resource type. This is preferably accomplished by performing a multi-variant regression analysis of selected actual instruction execution efficiency values in the pool of information or data.

Abstract: In particular, a system and method for receiving high speed processor bus traces for study of computer system capacity and operation uses a collection of coordinated collector system to collect trace data for a plurality of processor busses operating at the same time in a multiprocessor computer system under test. Pipelined bus communications on the processor bus are aligned, in one mode, and in another, multiple instructions on split domain busses are aligned. In both cases a time stamp is obtained to match each processor word to a time of occurrence to facilitate study of the trace data. All time stamps from the various busses being studied and from which trace data is being collected have the same values at any given time so that the data collected from each bus can be coordinated with data from the other busses of the plurality by the reading of the time stamps.

Abstract: A system and method for receiving high speed processor bus traces for study of computer system capacity and operation uses a small FIFO memory and skips unused bus cycles to avoid the requirement for memory speed to match the processor bus speed. Pipelined bus communications on the processor bus are aligned, in one mode, and in another, multiple instructions on split domain busses are aligned. In both cases a time stamp is obtained to match each processor word to a time of occurrence to facilitate study of the trace data.