Abstract: A system that generates brewed beverages may receive requests to produce specified brewed beverages. The system may include a scheduler that initiates and controls the performance of one or more chemical or mechanical processes to produce the beverages. While one chemical or mechanical process for producing a beverage is being performed, other processes may be performed for production of the beverage or another beverage. The scheduler may determine the time at which to perform each process, the time at which a beverage should be presented, the resources to be used to perform the processes, or the time at which to perform a cleaning process, dependent on an actual or expected demand for beverages, or dependent on a target time for beverage retrieval. Shared resources may be applied to the production of beverages for high priority orders, while partially completed beverages for lower priority orders are staged for subsequent advancement.

Abstract: An apparatus that generates brewed beverages by performing one or more chemical and/or mechanical processes may receive requests to produce specified brewed beverages. The apparatus may include a master controller that initiates and controls performance of the chemical and/or mechanical processes to produce the specified beverages. The master controller may adaptively apply one or more process accelerators during the performance of one of the chemical or mechanical processes to accelerate the process or to achieve a desired qualitative or quantitative characteristic for a beverage or a component thereof. The adaptive application of one or more process accelerators may be dependent on a multiple-variable process profile developed for the process and/or a specified beverage. For example, the pressure in a steam wand and/or the depth of the wand may be varied during a process to froth milk in order to produce frothed milk having a desired temperature.

Abstract: A system that generates brewed beverages may receive requests to produce specified brewed beverages. The system may include a scheduler that initiates and controls the performance of one or more chemical or mechanical processes to produce the beverages. While one chemical or mechanical process for producing a beverage is being performed, other processes may be performed for production of the beverage or another beverage. The scheduler may determine the time at which to perform each process, the time at which a beverage should be presented, the resources to be used to perform the processes, or the time at which to perform a cleaning process, dependent on an actual or expected demand for beverages, or dependent on a target time for beverage retrieval. Shared resources may be applied to the production of beverages for high priority orders, while partially completed beverages for lower priority orders are staged for subsequent advancement.

Abstract: An apparatus that generates brewed beverages by performing one or more chemical and/or mechanical processes may receive requests to produce specified brewed beverages. The apparatus may include a master controller that initiates and controls performance of the chemical and/or mechanical processes to produce the specified beverages. The master controller may adaptively apply one or more process accelerators during the performance of one of the chemical or mechanical processes to accelerate the process or to achieve a desired qualitative or quantitative characteristic for a beverage or a component thereof. The adaptive application of one or more process accelerators may be dependent on a multiple-variable process profile developed for the process and/or a specified beverage. For example, the pressure in a steam wand and/or the depth of the wand may be varied during a process to froth milk in order to produce frothed milk having a desired temperature.

Abstract: An apparatus that generates brewed beverages by performing one or more chemical and/or mechanical processes may receive requests to produce specified brewed beverages. The apparatus may include a master controller that initiates and controls performance of the chemical and/or mechanical processes to produce the specified beverages. The master controller may adaptively apply one or more process accelerators during the performance of one of the chemical or mechanical processes to accelerate the process or to achieve a desired qualitative or quantitative characteristic for a beverage or a component thereof. The adaptive application of one or more process accelerators may be dependent on a multiple-variable process profile developed for the process and/or a specified beverage. For example, the pressure in a steam wand and/or the depth of the wand may be varied during a process to froth milk in order to produce frothed milk having a desired temperature.

Abstract: A system that generates brewed beverages may receive requests to produce specified brewed beverages. The system may include a scheduler that initiates and controls the performance of one or more chemical or mechanical processes to produce the beverages. While one chemical or mechanical process for producing a beverage is being performed, other processes may be performed for production of the beverage or another beverage. The scheduler may determine the time at which to perform each process, the time at which a beverage should be presented, the resources to be used to perform the processes, or the time at which to perform a cleaning process, dependent on an actual or expected demand for beverages, or dependent on a target time for beverage retrieval. Shared resources may be applied to the production of beverages for high priority orders, while partially completed beverages for lower priority orders are staged for subsequent advancement.

Abstract: A system that generates brewed beverages may receive requests to produce specified brewed beverages. The system may include a scheduler that initiates and controls the performance of one or more chemical or mechanical processes to produce the beverages. While one chemical or mechanical process for producing a beverage is being performed, other processes may be performed for production of the beverage or another beverage. The scheduler may determine the time at which to perform each process, the time at which a beverage should be presented, the resources to be used to perform the processes, or the time at which to perform a cleaning process, dependent on an actual or expected demand for beverages, or dependent on a target time for beverage retrieval. Shared resources may be applied to the production of beverages for high priority orders, while partially completed beverages for lower priority orders are staged for subsequent advancement.

Abstract: A method and apparatus to allow dynamic port provisioning of communication ports within a Programmable Logic Device (PLD). The dynamic port provisioning combines configuration of serial Input/Output (I/O) devices with simultaneous reconfiguration of a portion of programmable logic resources within the PLD and processor functions to implement a particular communication protocol. The dynamic port provisioning is facilitated for a single channel, without affecting the dynamic port provisioning of other communication channels operating within the PLD.

Abstract: According to particular example embodiments, an integrated circuit includes one or more serializing data transmitters. Each such data transmitter is arranged to transmit data on a respective data output port of the integrated circuit, wherein the respective data output port for at least one of the data transmitters is dedicated to transmitting periodic data used for clocking a respective target circuit. In other particular embodiments involving feedback, phase-locked loop (PLL) signal control and/or delay-locked loop (DLL) signal control is achieved in functional blocks of a programmable logic device (PLD). The PLD is responsive to a source clock and includes a configurable logic array that includes configurable logic blocks and configurable routing blocks, and the respective data output port for at least one of the data transmitters provides a respective target clock.

Abstract: A method and apparatus to provide various mechanisms to improve yield of an integrated circuit (IC) employing serial input/output (I/O) communication devices. A single error correction model provides one spare transceiver per group of primary transceivers, whereby reconfiguration of the IC isolates the defective transceiver and configures the replacement transceiver for operation in its place. A multiple error correction model is also provided, whereby multiple replacement transceivers may be configured to replace multiple defective transceivers. The replacement mechanism may occur during various phases of the IC, such as during wafer testing, final testing, or post-deployment testing.

Abstract: A voltage controlled oscillator (VCO) having a single stage ring-oscillator having both coarse and fine control of the frequency of oscillation is described. In an embodiment the VCO may include a first n-channel latch having a first output and a second output; a first P-channel transistor coupled between a voltage supply and a first VCO output, where a gate of the first P-channel transistor is coupled to the first output of the first n-channel latch; a first programmable resistor circuit coupled between the first VCO output and the first output of the first n-channel latch; and a second n-channel latch coupled to the first VCO output.

Abstract: A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (I216) that is first conducted by a resistor (310) of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor (306) of the RC network from node (320). A second current path multiplies the current conducted by capacitor (306) by a first current multiplication factor. A third current path provides current to a second charge pump, which multiplies the current from the first charge pump by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor (306).

Abstract: A VCO (110) can be configured to convert an analog input signal (105) to a digital output signal (125). In accordance with the inventive arrangements, the VCO can convert the analog input signal to at least one intermediate signal (130) having a frequency dependent on the analog input signal. A frequency detector (115) can be configured to determine a frequency of at least one intermediate signal. Subsequently, a mapping circuit (120) can be configured to map the determined frequency of the at least one intermediate signal to an output value representing the digital output signal (125).

Abstract: An integrated circuit includes analog test cells to determine if an analog signal is within a predetermined voltage or current range. The test cell uses one or more analog reference signals to establish boundaries of a test range. Different embodiments of the analog test cells selectively test multiple analog signals provided in an integrated circuit. A test system can be provided to test multiple analog signals of an integrated circuit by scanning multiple analog test cells distributed throughout the integrated circuit and providing the test data for analysis. An analog circuit of an integrated circuit can be tested at different stages in manufacturing, including during a wafer stage prior to separation of individual circuit dice. Further, analog circuitry can be tested and characterized without the need for analog or digital/analog testers. In contrast, a digital only tester can be used to test analog circuitry.

Abstract: In this invention, three schemes of nonvolatile FPLD structures are proposed using a latch that has been disclosed herein. In the first proposed scheme the latches, which can be designed using either GMR or SDT devices, will work as interconnects in a conventional Programmable Logic Array (PLA). In the second proposed scheme, the latches will constitute the look-up table for a standard PLA. In the third proposed scheme, the latch itself will work as a nonvolatile Programmable Logic Device (PLD) structure. This FPLD latch will have 2n GMR or SDT resistors, instead of just 2, for an n-input logic gate. By programming the resistors differently, in each scheme, numerous different logic functions from the same logic gate can be achieved.

Abstract: An integrated circuit includes analog test cells to determine if an analog signal is within a predetermined voltage or current range. The test cell uses one or more analog reference signals to establish boundaries of a test range. Different embodiments of the analog test cells selectively test multiple analog signals provided in an integrated circuit. A test system can be provided to test multiple analog signals of an integrated circuit by scanning multiple analog test cells distributed throughout the integrated circuit and providing the test data for analysis. An analog circuit of an integrated circuit can be tested at different stages in manufacturing, including during a wafer stage prior to separation of individual circuit dice. Further, analog circuitry can be tested and characterized without the need for analog or digital/analog testers. In contrast, a digital only tester can be used to test analog circuitry.

Abstract: A segmented digital-to-analog converter (DAC) has been described that uses a two-step calibration process to calibrate current sources to a single primary reference source. In one embodiment, the DAC includes sub-DACs, a reference generator circuit and a primary, or golden, reference source. Current sources of both the sub-DACs and the reference generator are calibrated to a golden current source or primary reference current. In one embodiment, the current sources each include a transistor coupled so that a gate voltage can be adjusted during calibration. The multiple current sources of the reference generator are first calibrated to the primary reference source. The calibrated output currents of the reference generator are then used to calibrate current sources in the sub-DACs.

Abstract: A device and method for sensing the status of a non-volatile magnetic latch. A cross-coupled inverter pair latch cell is employed for the data sensing. During the ‘Sense’ cycles, the inputs to the latch cell are from spin dependent tunneling effect devices, each located in its respective inverter pair. The SDT magneto-resistive storage devices have complimentary resistance states written into them. A switch, connected to the inverter pairs, is used to reset and initiate a regenerative sequence. Whenever the switch is turned on (reset) and off (regenerate), the latch cell will sense a potential imbalance generated by the magneto-resistive storage devices with complimentary resistance. During regeneration, the imbalance will be amplified and eventually the inverter pairs will reach a logic high or logic low state. The latch can be used as a memory circuit, however, upon loss of power the memory is retained. The state of the circuit is retained inside of SDT components.

Abstract: A device and method for sensing the status of a non-volatile magnetic latch. A cross-coupled inverter pair latch cell is employed for the data sensing. During the ‘Sense’ cycles, the inputs to the latch cell are from Giant Magneto-Resistive effect devices, each located in its respective inverter pair. The magneto-resistive storage devices have complimentary resistance states written into them. A switch, connected to the inverter pairs, is used to reset and initiate a regenerative sequence. Whenever the switch is turned on (reset) and off (regenerate), the latch cell will sense a potential imbalance generated by the magneto-resistive storage devices with complimentary resistance. During regeneration, the imbalance will be amplified and eventually the inverter pairs will reach a logic high or logic low state. The latch can be used as a memory circuit, however, upon loss of power the memory is retained. The state of the circuit is retained inside of GMR components.

Abstract: A controller for a power converter wherein there is provided a comparator having an output terminal and first and second input terminals. A switch-mode power train is coupled to the output terminal and operable to receive an unregulated input voltage and provide a regulated output voltage. A feedback network coupled to the switch-mode power train provides a voltage to the first input of the comparator. A ramp circuit includes a first capacitor divider having a first capacitor connected from a first input node to a first midpoint node and a second capacitor connected from the first midpoint node to a first reference voltage node and a second capacitor divider including a third capacitor connected from a second input node to a second midpoint node and a fourth capacitor connected from the second midpoint node to the first reference node. A first switch couples the first or second midpoint node to the second input of said comparator.