Abstract: A technique is provided for forming a circuitized substrate which substantially reduces defects in a circuit board formed of multiple layers of dielectric material on each of which layers electrical circuitry is formed. Each layer of dielectric material is formed of two distinct and separate coatings or sheets or films of a photopatternable dielectric material which is photoformed to provide through openings to the layer of circuitry below and then plated with the desired circuitry including plating in the photoformed openings to form vias. In this way if there is a pin hole type defect in either coating or sheet of dielectric material, in all probability it will not align with a similar defect in the other sheet or coating of the dielectric layer, thus preventing unwanted plating extending from one layer of circuitry to the underlying layer of circuitry.

Abstract: A technique is provided for forming a circuitized substrate which substantially reduces defects in a circuit board formed of multiple layers of dielectric material on each of which layers electrical circuitry is formed. Each layer of dielectric material is formed of two distinct and separate coatings or sheets or films of a photopatternable dielectric material which is photoformed to provide through openings to the layer of circuitry below and then plated with the desired circuitry including plating in the photoformed openings to form vias. In this way if there is a pin hole type defect in either coating or sheet of dielectric material, in all probability it will not align with a similar defect in the other sheet or coating of the dielectric layer, thus preventing unwanted plating extending from one layer of circuitry to the underlying layer of circuitry.

Abstract: The present invention relates to a method for planarizing circuit board apertures wherein a photoimageable film composition comprising a photoimageable dielectric composition and a support film is employed to fill the circuit board apertures. Precircuitized and postcircuitized embodiments are discussed.

Abstract: According to the present invention, a technique for controlling the flow of plastic encapsulant which is applied over an integrated circuit (I/C) chip wire bonded to wire pads formed on a chip carrier substrate is provided. This technique includes applying a barrier material to the substrate surrounding the wire bond pads, which barrier material is in the form of two walls projecting upwardly from the surface thereof, and defining a well between the walls to confine the flow of the encapsulant material. This prevents the encapsulant material from flowing past a desired defined boundary and covering the circuit connection pads which are not intended to be covered.

Abstract: According to the present invention, a technique for controlling the flow of plastic encapsulant which is applied over an integrated circuit (I/C) chip wire bonded to wire pads formed on a chip carrier substrate is provided. This technique includes applying a barrier material to the substrate surrounding the wire bond pads, which barrier material is in the form of two walls projecting upwardly from the surface thereof, and defining a well between the walls to confine the flow of the encapsulant material. This prevents the encapsulant material from flowing past a desired defined boundary and covering the circuit connection pads which are not intended to be covered.