Abstract: A bond pad support structure for a semiconductor device comprises at least two metal layers subjacent an uppermost passivation layer on the device. An opening through the passivation layer exposes a top surface of a top metal layer. A metal feature is formed in an insulating layer, disposed between the two metal layers, and divides the insulating layer into a plurality of discrete sections. The metal feature includes a plurality of intersecting metal-filled recesses that interconnect the two metal layers. At least a portion of the metal feature is disposed within a cross-sectional area defined as a perimeter of a periphery of the opening.

Abstract: A method and apparatus for measuring Kelvin contact resistance within an integrated circuit interconnect is provided, having upper and lower Kelvin contact resistance contacts covering a via and interconnect being measured, along with a third conductor placed substantially between the upper and lower Kelvin contacts, and in contact with the via.

Abstract: The present invention utilizes a selective overlayer to provide more efficient fabrication of a dual damascene multilevel interconnect structure. The selective overlayer serves as a protective mask which prevents the upper layer of the composite layer from being eroded during the formation of the multi-level interconnects. The present invention also solves some of the problems associated with the full-via first and partial-via first fabrication methods because the selective overlayer enables an efficient, deep partial via to be formed while preventing the deposit of undeveloped photoresist in subsequent fabrication steps. The present invention also provides advantages during the planarization and polishing of the dual damascene structure after the deposition of the conductive layer because the selective overlayer allows for efficient planarization without loss of trench depth control.