Abstract: Provided is a process for manufacturing a diamond like carbon layer. The process for manufacturing the diamond like carbon layer includes, without limitation, forming a layer of diamond like carbon over a substrate, and reactive ion etching the layer of diamond like carbon.

Abstract: Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a first semiconductor layer over a substrate, and forming a second semiconductor layer over the first semiconductor layer, wherein an amorphous nitrided silicon adhesion layer is located between and adheres the first and second semiconductor layers.

Abstract: Provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, without limitation, includes forming a first semiconductor layer over a substrate, and forming a second semiconductor layer over the first semiconductor layer, wherein an amorphous nitrided silicon adhesion layer is located between and adheres the first and second semiconductor layers.

Abstract: Provided, in one embodiment, is a method for manufacturing a resistive structure. This method, without limitation, includes forming a substrate, and forming a tantalum-aluminum-nitride resistive layer over the substrate. Moreover, a bulk resistivity of the tantalum-aluminum-nitride resistive layer may be adjusted by varying at least one deposition condition selected from the group consisting of a flow rate ratio of nitrogen to argon, power, pressure, temperature and radio frequency (RF) bias voltage.

Abstract: Provided is a process for manufacturing a diamond like carbon layer. The process for manufacturing the diamond like carbon layer includes, without limitation, forming a layer of diamond like carbon over a substrate, and reactive ion etching the layer of diamond like carbon.

Abstract: Provided is a method for removing diamond like carbon residue from a deposition chamber. This method, in one embodiment, may include subjecting a deposition chamber including diamond like carbon residue to a plasma clean in the presence of fluorine containing gas and oxygen containing gas. The method may further include purging the deposition chamber having been subjected to the plasma clean with an inert gas, and pumping the deposition chamber having been subjected to the plasma clean.

Abstract: A thermal inkjet printhead 100 of the present invention includes a heating element 110, an ink chamber, control circuitry 108, an ink reservoir, and a memory array 106. The control circuitry 108 causes the heating element to generate thermal energy thereby causing ink within the ink chamber to generate bubbles of ink, which are then expelled through a nozzle. The ink reservoir replenishes used ink in the ink chamber. The memory array 106 stores and provides the identification parameters for the thermal inkjet printhead 100. The identification parameters are typically provided during initialization of the printer and include color(s) of ink (e.g., black, green, red, blue), a number of nozzles on the thermal inkjet printhead, an addressing frequency, nozzle spacing, heating architecture, and the like.

Abstract: A thermal inkjet printhead 100 of the present invention includes a heating element 110, an ink chamber, control circuitry 108, an ink reservoir, and a memory array 106. The control circuitry 108 causes the heating element to generate thermal energy thereby causing ink within the ink chamber to generate bubbles of ink, which are then expelled through a nozzle. The ink reservoir replenishes used ink in the ink chamber. The memory array 106 stores and provides the identification parameters for the thermal inkjet printhead 100. The identification parameters are typically provided during initialization of the printer and include color(s) of ink (e.g., black, green, red, blue), a number of nozzles on the thermal inkjet printhead, an addressing frequency, nozzle spacing, heating architecture, and the like.

Abstract: A thermal inkjet printhead 100 of the present invention includes a heating element 110, an ink chamber, control circuitry 108, an ink reservoir, and a memory array 106. The control circuitry 108 causes the heating element to generate thermal energy thereby causing ink within the ink chamber to generate bubbles of ink, which are then expelled through a nozzle. The ink reservoir replenishes used ink in the ink chamber. The memory array 106 stores and provides the identification parameters for the thermal inkjet printhead 100. The identification parameters are typically provided during initialization of the printer and include color(s) of ink (e.g., black, green, red, blue), a number of nozzles on the thermal inkjet printhead, an addressing frequency, nozzle spacing, heating architecture, and the like.

Abstract: A thermal inkjet printhead 100 of the present invention includes a heating element 110, an ink chamber, control circuitry 108, an ink reservoir, and a memory array 106. The control circuitry 108 causes the heating element to generate thermal energy thereby causing ink within the ink chamber to generate bubbles of ink, which are then expelled through a nozzle. The ink reservoir replenishes used ink in the ink chamber. The memory array 106 stores and provides the identification parameters for the thermal inkjet printhead 100. The identification parameters are typically provided during initialization of the printer and include color(s) of ink (e.g., black, green, red, blue), a number of nozzles on the thermal inkjet printhead, an addressing frequency, nozzle spacing, heating architecture, and the like.

Abstract: The present invention provides a non-global process for designing an integrated circuit layout. The process comprises locating an isolated layout feature of an integrated circuit layout and non-globally changing at least one lateral dimension of the isolated layout feature to obtain an optimized increment. The change in lateral dimension by the optimized increment does not violate a minimum separation distance between the isolated layout feature and the other adjacent layout features. The process may be incorporated into a system for non-globally modifying an integrated circuit layout, described in a data file or an integrated circuit design system.

Abstract: The present invention provides a non-global process for designing an integrated circuit layout. The process comprises locating an isolated layout feature of an integrated circuit layout and non-globally changing at least one lateral dimension of the isolated layout feature to obtain an optimized increment. The change in lateral dimension by the optimized increment does not violate a minimum separation distance between the isolated layout feature and the other adjacent layout features. The process may be incorporated into a system for non-globally modifying an integrated circuit layout, described in a data file or an integrated circuit design system.