Patents by Inventor Marzio Pedrali-Noy
Marzio Pedrali-Noy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7880554Abstract: A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In an exemplary embodiment, the device includes a reference clock oscillator, a low-jitter oscillator, a power supply including a clock signal input to regulate a power supply voltage for the low-jitter oscillator, a clock detector to generate a clock detector control signal when the low-jitter oscillator output frequency is stable, and a multiplexer to select between a reference clock oscillator output signal and a low-jitter oscillator output signal as the clock signal input to the power supply to mitigate effects of period jitter in the low-jitter oscillator output signal when the clock detector control signal is asserted.Type: GrantFiled: April 29, 2009Date of Patent: February 1, 2011Assignee: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Publication number: 20100283552Abstract: An oscillator is disclosed. The oscillator includes a first capacitor. The oscillator also includes a second capacitor. The oscillator further includes a first current source. The oscillator also includes a second current source. The oscillator further includes a comparator that has a first input and a second input. The oscillator also includes a reference node. The oscillator further includes a controller that is configured to selectively couple the first current source to the first capacitor and the second current source to the reference node during a first time period.Type: ApplicationFiled: May 6, 2010Publication date: November 11, 2010Applicant: QUALCOMM INCORPORATEDInventors: Sylvain M. Colin, Jun Young Park, Marzio Pedrali Noy
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Publication number: 20100271140Abstract: A supply-regulated Phase-locked loop (PLL) is provided. The PLL comprises a supply-regulating loop, a voltage-controlled oscillator (VCO), and a programmable decoupling capacitor array for the VCO. The capacitance of the VCO decoupling capacitor array is adjustable to be equal to N times CUNIT, where N is the current value of a multiplication factor of a divide-by-N circuit and CUNIT is a unit capacitance characterized for a processing technology chosen for fabricating the decoupling capacitor array. When the PLL switches from one frequency band to another, a higher-order pole introduced by the VCO decoupling capacitor tracks the PLL reference frequency, thus improving the PLL operational stability.Type: ApplicationFiled: April 26, 2009Publication date: October 28, 2010Applicant: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Publication number: 20100194471Abstract: A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In an exemplary embodiment, the device includes a reference clock oscillator, a low-jitter oscillator, a power supply including a clock signal input to regulate a power supply voltage for the low-jitter oscillator, a clock detector to generate a clock detector control signal when the low-jitter oscillator output frequency is stable, and a multiplexer to select between a reference clock oscillator output signal and a low-jitter oscillator output signal as the clock signal input to the power supply to mitigate effects of period jitter in the low-jitter oscillator output signal when the clock detector control signal is asserted.Type: ApplicationFiled: April 29, 2009Publication date: August 5, 2010Applicant: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Patent number: 7724092Abstract: A dual-path current amplifier having a slow high-gain path and a fast low-gain path is described. In one design, the slow high-gain path is implemented with a positive feedback loop and has a gain of greater than one and a bandwidth determined by a pole. The fast low-gain path has unity gain and wide bandwidth. The two signal paths receive an input current and provide first and seconds currents. A summer sums the first and second currents and provides an output current for the dual-path current amplifier. The dual-path current amplifier may be implemented with first and second current mirrors. The first current mirror may implement the fast low-gain path. The first and second current mirrors may be coupled together and implement the slow high-gain path. The first current mirror may be implemented with P-FETs. The second current mirror may be implemented with N-FETs, an operational amplifier, and a capacitor.Type: GrantFiled: October 3, 2007Date of Patent: May 25, 2010Assignee: QUALCOMM, IncorporatedInventors: Xiaohong Quan, Marzio Pedrali-Noy
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Publication number: 20100117701Abstract: Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump output noise in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a phase frequency detector (PFD) providing a phase comparison operation, a loop filter providing a control voltage to lock the VCO to a desired operating frequency, and a charge pump configured to provide an output signal to the loop filter in response to at least one of an UP pulse and a DOWN pulse. The apparatus further includes a sampling switch, coupled between an input of the loop filter, an output of the charge pump, and characterized by a sampling interval.Type: ApplicationFiled: February 9, 2009Publication date: May 13, 2010Applicant: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Publication number: 20100117700Abstract: Techniques for adaptively control of a loop filter sampling interval to mitigate the effects of charge pump leakage current in an apparatus including a phase lock loop circuit are provided. In one aspect, the apparatus includes a voltage controlled oscillator (VCO), a phase frequency detector (PFD) providing a phase comparison operation, a loop filter providing a control voltage to lock the VCO to a desired operating frequency, and a charge pump configured to provide an output signal to the loop filter in response to at least one of an UP pulse and a DOWN pulse. The apparatus further includes a sampling switch, coupled between an input of the loop filter, an output of the charge pump, and characterized by a sampling interval.Type: ApplicationFiled: February 9, 2009Publication date: May 13, 2010Applicant: QUALCOMM IncorporatedInventors: Ashwin Raghunathan, Marzio Pedrali-Noy
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Publication number: 20090160519Abstract: A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit couples to the first delay circuit and provides a second delay of a fraction of one time unit. The first delay circuit may include multiple unit delay cells coupled in series. Each unit delay cell may provide a delay of one time unit when enabled. The second delay circuit may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate that provides extra loading to obtain the longer delay for the second path.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Applicant: QUALCOMM INCORPORATEDInventors: Mustafa Keskin, Marzio Pedrali-Noy
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Publication number: 20090091393Abstract: A dual-path current amplifier having a slow high-gain path and a fast low-gain path is described. In one design, the slow high-gain path is implemented with a positive feedback loop and has a gain of greater than one and a bandwidth determined by a pole. The fast low-gain path has unity gain and wide bandwidth. The two signal paths receive an input current and provide first and seconds currents. A summer sums the first and second currents and provides an output current for the dual-path current amplifier. The dual-path current amplifier may be implemented with first and second current mirrors. The first current mirror may implement the fast low-gain path. The first and second current mirrors may be coupled together and implement the slow high-gain path. The first current mirror may be implemented with P-FETs. The second current mirror may be implemented with N-FETs, an operational amplifier, and a capacitor.Type: ApplicationFiled: October 3, 2007Publication date: April 9, 2009Applicant: QUALCOMM IncorporatedInventors: Xiaohong Quan, Marzio Pedrali-Noy
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Publication number: 20090079483Abstract: Delay circuits capable of providing delays closely matching propagation delays of synchronous circuits are described. In one design, an apparatus includes a synchronous circuit and a delay circuit. The synchronous circuit includes a forward path from a data input to a data output. The synchronous circuit receives input data and provides output data with a propagation delay. The delay circuit receives an input signal and provides a delayed input signal having a delay matching the propagation delay of the synchronous circuit. The delay circuit includes at least two logic gates in the forward path of the synchronous circuit. The synchronous and delay circuits may be implemented based on the same or similar circuit architecture. The delay circuit may be based on a replica of the synchronous circuit, with the replica having feedback loops broken and clock input coupled to appropriate logic value to always enable the delay circuit.Type: ApplicationFiled: September 24, 2007Publication date: March 26, 2009Applicant: QUALCOMM INCORPORATEDInventors: Mustafa Keskin, Marzio Pedrali-Noy
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Publication number: 20070159262Abstract: Techniques to effectively handle large voltage-controlled oscillator (VCO) gain are described. The techniques utilize (1) a slow high-gain path to provide an average control current that adjusts the center frequency of a VCO and (2) a fast low-gain path to provide an instantaneous control current that adjusts the VCO frequency during normal operation. In one design, the VCO includes a voltage-to-current converter, a current amplifier, a summer, and a current-controlled oscillator (ICO). The voltage-to-current converter receives a control voltage and generates a first current and a second current. The current amplifier amplifies and filters the first current and generates a third current. The summer sums the second current and the third current and generates a control current. The ICO receives the control current and generates an oscillator signal having a frequency determined by the control current.Type: ApplicationFiled: April 7, 2006Publication date: July 12, 2007Inventors: Xiaohong Quan, Marzio Pedrali-Noy
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Patent number: 7148460Abstract: An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.Type: GrantFiled: March 25, 2004Date of Patent: December 12, 2006Assignee: The Regents of the University of CaliforniaInventors: William W. Moses, Eric Beuville, Marzio Pedrali-Noy
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Publication number: 20040251400Abstract: An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.Type: ApplicationFiled: March 25, 2004Publication date: December 16, 2004Inventors: William W. Moses, Eric Beuville, Marzio Pedrali-Noy
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Patent number: 6737627Abstract: An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.Type: GrantFiled: September 27, 2001Date of Patent: May 18, 2004Assignee: The Regents of the University of CaliforniaInventors: William W. Moses, Eric Beuville, Marzio Pedrali-Noy
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Publication number: 20020074504Abstract: An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.Type: ApplicationFiled: September 27, 2001Publication date: June 20, 2002Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: William W. Moses, Eric Neuville, Marzio Pedrali-Noy