Patents by Inventor Masaaki Hara

Masaaki Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070211320
    Abstract: A hologram recording apparatus includes a signal-beam spatial light modulating section, a reference-beam spatial light modulating section, and a control unit. A signal beam pattern generates a signal beam. A reference beam pattern generates a reference beam. The control unit controls the shapes of the two beam patterns. A data-recording signal beam pattern is displayed on the signal-beam spatial light modulating section and a data-recording reference beam pattern is displayed on the reference-beam spatial light modulating section so that a data-recording hologram is formed in a predetermined area of a holographic recording medium. An encryption signal beam pattern for encrypting the data-recording hologram is displayed on the signal-beam spatial light modulating section and an encryption reference beam pattern is displayed on the reference-beam spatial light modulating section so that an encryption hologram is formed in the same area as the predetermined area of the holographic recording medium.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 13, 2007
    Applicant: SONY CORPORATION
    Inventors: Mitsuru Toishi, Masaaki Hara
  • Patent number: 7244514
    Abstract: A corrosion resistant part comprises an aluminum alloy part main body, an alumite layer disposed on the part main body, and a corrosion resistant layer disposed on the alumite layer. The part main body has a normal portion and a flawed portion so that the alumite layer comprises a normal portion alumite layer formed on the normal portion and a flawed portion alumite layer formed on the flawed portion, and the corrosion resistant layer comprises a normal portion corrosion resistant layer formed on the normal portion and a flawed portion corrosion resistant layer formed on the flawed portion. The normal portion alumite layer has a thickness between approximately 0.5 microns and approximately 5.0 microns. The corrosion resistant layer is formed from an ionic resin and has a thickness less than or equal to approximately 5 microns.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: July 17, 2007
    Assignee: Shimano, Inc.
    Inventors: Masaaki Hara, Wataru Yamauchi, Kenji Matsuda, Masayoshi Kihara
  • Publication number: 20070159365
    Abstract: Disclosed herein is a data identification method for identifying, from within a readout signal from a recording medium on or in which user data of k bits are recorded using a recording modulation code wherein m bits from among n bits which compose one codeword have a value of “1” while the remaining n-m bits have another value of “0”, the data, n and m being integers including, a first step of delimiting the readout signal in a unit of a codeword and adding, with regard to one of the n-bit codewords obtained by the delimiting, an amplitude of the readout signal of the bits of “1” to 2ˆk different codewords which may possibly be recorded and setting results of the addition as evaluation values, and a second step of finding a maximum value among the 2ˆk evaluation values and outputting the maximum value as an evaluation result.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 12, 2007
    Inventors: Masaaki Hara, Kenji Tanaka
  • Publication number: 20070159364
    Abstract: A data identification method including: a first step; a second step; a third step; and a fourth step, and the third and fourth steps being repeated until an identification result included in the table of recording modulation codes is obtained at the third step.
    Type: Application
    Filed: December 22, 2006
    Publication date: July 12, 2007
    Inventor: Masaaki Hara
  • Patent number: 7221600
    Abstract: An arithmetic circuit is provided having a compact and high-speed logic-in-memory wherein various operations are performed. The arithmetic circuit includes a memory element having a variable resistance element R in which the state of resistance changes reversibly between the state of high resistance and the state of low resistance by applying voltages with different polarities between one electrode and the other electrode, and at least one transistor of MRD, MRS, MW1 and MW2 connected respectively to both ends of the memory element; wherein data is stored in the memory element, the operation for the external data X, W, Y1 and Y2 input through any of the transistors is performed by applying potential to each of the ends of the memory element through the transistors MRD, MRS, MW1, and MW2, and a result of the operation is output from the memory element.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: May 22, 2007
    Assignee: Sony Corporation
    Inventors: Masaaki Hara, Nobumichi Okazaki
  • Patent number: 7209425
    Abstract: An apparatus for driving a tape-shaped optical recording medium, which comprises a supply reel (41) for supplying an optical tape (40), a take-up reel (42) for taking-up the optical tape (40), a friction capstan (43) for driving the optical tape (40) to run to the take-up reel (42) from the supply reel (41) and a running guide member (46) for guiding the optical tape (40) running between the supply reel (41) and the take-up reel (42). The running guide member (46) has a flat portion forming a guide face portion (70) for facing to the optical tape (40) is operative to cause the optical tape (40) to run along the flat portion. Thereby, an area on the guide face portion (70) of the running guide member (46) where an incident position on the optical tape (40) of a light beam is fixed invariably can be stably maintained to be relatively wide.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: April 24, 2007
    Assignee: Sony Corporation
    Inventors: Masaaki Hara, Jun Sawai, Yujiro Ito
  • Publication number: 20070068750
    Abstract: A bicycle disc brake pad is used in a disc brake device and is configured to reduce restrictions on backplate material in a disc brake pad for a bicycle in which a friction member is bonded to a backplate by a diffusion bonding method. The bicycle disc brake pad has a backplate, a spray coating layer and a friction member. The surface of the backplate has a spray coat surface. The spray coating layer is a copper or copper alloy layer formed on the spray coat surface. The friction member is bonded to the spray coating layer by a diffusion bonding method. Preferably, the spray coat surface of the backplate is formed with a rough surface on at least part of the spray coat surface.
    Type: Application
    Filed: June 14, 2006
    Publication date: March 29, 2007
    Applicant: Shimano Inc.
    Inventors: Masaaki Hara, Toru Iwai, Takashi Fujitani, Tsukasa Fukuta
  • Publication number: 20070067701
    Abstract: A recording control device that controls data recording in a recording medium including a plurality of recording blocks each composed of a plurality of recording units as a unit of the data recording, the recording control device comprising a recording controller configured to temporarily record after-error data in one recording block of the plurality of recording blocks as a save block if a predetermined recording block of the plurality of recording blocks has become a defective block in which the data recording is impossible due to occurrence of an error at a certain recording unit during sequential recording of data in recording units from a beginning recording unit in the predetermined recording block, the after-error data being data that originally should be recorded in the certain recording unit and in the recording unit subsequent to the certain recording unit in the predetermined recording block.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 22, 2007
    Inventors: Tsutomu Shimosato, Jun Sawai, Masaaki Hara
  • Patent number: 7111910
    Abstract: A rim material having a non-uniform thickness, a rim manufactured from the rim material, and a method for manufacturing the rim from the rim material. The rim material includes a first material portion which forms an axially curved portion of the rim after the rim material is formed to the rim and a second material portion which forms an intermediate portion between adjacent axially curved portions after the rim material is formed to the rim. The first material portion has a thick parallel-surface portion including opposite surfaces parallel to each other. The parallel-surface portion has a width greater than a maximum amount of an axial dislocation of the parallel-surface portion expected to occur when the parallel-surface portion is formed to a corresponding curved portion. The second material portion has a thickness varying portion. The thickness varying portion includes a surface having a configuration defined by a line including a straight line and/or a slightly curved line.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: September 26, 2006
    Assignee: Topy Kogyo Kabushiki Kaisha
    Inventors: Kishiro Abe, Tsuneo Watanabe, Satoru Miyashita, Takenobu Hasegawa, Kenichi Inada, Shojiro Yokomizo, Shingo Tsukui, Katsuki Kato, Morishi Kunou, Katsunori Todoko, Kenji Hayashi, Nobuyuki Soma, Masaaki Hara
  • Publication number: 20060092691
    Abstract: A memory element having a configuration in which contents of recorded data can be judged easily and power consumption can be reduced, and a method of driving the same are provided. A memory element 10 of the present invention includes variable resistance elements 11 and 12 whose resistance state changes reversibly between a high resistance state and a low resistance state by applying a voltage of a different polarity between an electrode 1 of one side and an electrode 2 of the other side; the electrode 1 of one side in each element of the two variable resistance elements 11 and 12 is made a common electrode; and the electrode 2 of the other side in each element of the two variable resistance elements 11 and 12 is made independent and is provided respectively with the terminal X and terminal Y, to form a memory cell having two terminals in total.
    Type: Application
    Filed: November 2, 2005
    Publication date: May 4, 2006
    Applicant: Sony Corporation
    Inventors: Tsunenori Shiimoto, Katsuhisa Aratani, Masaaki Hara, Tomohito Tsushima
  • Patent number: 7035136
    Abstract: A nonvolatile magnetic memory device having a nonvolatile magnetic memory array comprising write-in word line(s), bit lines and tunnel magnetoresistance devices, wherein when data is written into the tunnel magnetoresistance device, a current I(m)RWL is passed through the m-th-place write-in word line, a current g(0)·I(n)BL is passed through the n-th-place bit line, and at the same time, a current g(k)·I(n)BL is passed through the q-th-place bit line (q=n+k, k is ±1, ±2, . . . , and the total number of the lines is K), and a spatial FIR filter assuming magnetic fields, which are supposed to be formed in the n-th-place bit line and the bit lines that are K in number by the current I(n)BL, to be discrete pulse response and assuming the coefficients g(0) and g(k) to be tap-gains is constituted of the n-th-place bit line and the bit lines that are K in number.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: April 25, 2006
    Assignee: Sony Corporation
    Inventors: Masaaki Hara, Tsunenori Shiimoto, Yujiro Ito, Jun Sawai
  • Patent number: 7002838
    Abstract: A semiconductor storage device has an array of memories, which store data and which are arranged in a matrix, and can read the data in response to address designation. The semiconductor storage device includes word line pairs, bit line pairs, and resistance portions. The resistance portions are each connected across two word lines of the corresponding word line pair and two bit lines of the corresponding bit line at the corresponding intersection thereof. Each resistance portion includes resistors having differential values in both the word line direction and the bit line direction. This arrangement allows the semiconductor storage device to read data with accuracy at high speed and allows the semiconductor storage device to be miniaturized at low cost.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: February 21, 2006
    Assignee: Sony Corporation
    Inventors: Tsunenori Shiimoto, Masaaki Hara
  • Publication number: 20060028247
    Abstract: An arithmetic circuit having a high versatility, with which such a circuit as a compact and high-speed logic-in-memory is obtained and various operations is performed, is provided. The arithmetic circuit includes a memory element having a variable resistance element R in which the state of resistance changes reversibly between the state of high resistance and the state of low resistance by applying voltages with different polarities between one electrode and the other electrode, and at least one transistor of MRD, MRS, MW1 and MW2 connected respectively to both ends of the memory element; wherein data is stored in the memory element, the operation for the external data X, W, Y1 and Y2 input through any of the transistors is performed by applying potential to each of the ends of the memory element through the transistors MRD, MRS, MW1, and MW2, and a result of the operation is output from the memory element.
    Type: Application
    Filed: July 21, 2005
    Publication date: February 9, 2006
    Applicant: Sony Corporation
    Inventors: Masaaki Hara, Nobumichi Okazaki
  • Publication number: 20050260424
    Abstract: A corrosion resistant part comprises an aluminum alloy part main body, an alumite layer disposed on the part main body, and a corrosion resistant layer disposed on the alumite layer. The part main body has a normal portion and a flawed portion so that the alumite layer comprises a normal portion alumite layer formed on the normal portion and a flawed portion alumite layer formed on the flawed portion, and the corrosion resistant layer comprises a normal portion corrosion resistant layer formed on the normal portion and a flawed portion corrosion resistant layer formed on the flawed portion. The normal portion alumite layer has a thickness between approximately 0.5 microns and approximately 5.0 microns. The corrosion resistant layer is formed from an ionic resin and has a thickness less than or equal to approximately 5 microns.
    Type: Application
    Filed: November 29, 2004
    Publication date: November 24, 2005
    Applicant: SHIMANO, INC.
    Inventors: Masaaki Hara, Wataru Yamauchi, Kenji Matsuda, Masayoshi Kihara
  • Publication number: 20050253447
    Abstract: A rim material having a non-uniform thickness, a rim manufactured from the rim material, and a method for manufacturing the rim from the rim material. The rim material includes a first material portion which forms an axially curved portion of the rim after the rim material is formed to the rim and a second material portion which forms an intermediate portion between adjacent axially curved portions after the rim material is formed to the rim. The first material portion has a thick parallel-surface portion including opposite surfaces parallel to each other. The parallel-surface portion has a width greater than a maximum amount of an axial dislocation of the parallel-surface portion expected to occur when the parallel-surface portion is formed to a corresponding curved portion. The second material portion has a thickness varying portion. The thickness varying portion includes a surface having a configuration defined by a line including a straight line and/or a slightly curved line.
    Type: Application
    Filed: July 27, 2005
    Publication date: November 17, 2005
    Inventors: Kishiro Abe, Tsuneo Watanabe, Satoru Miyashita, Takenobu Hasegawa, Kenichi Inada, Shojiro Yokomizo, Shingo Tsukui, Katsuki Kato, Morishi Kunou, Katsunori Todoko, Kenji Hayashi, Nobuyuki Soma, Masaaki Hara
  • Publication number: 20050217417
    Abstract: A bicycle crank arm is provided that is a light, highly strong, highly rigid and highly designed in a complex shape. The bicycle crank arm has a crank axle mounting end portion, a central crank body portion and a pedal mounting end portion. The hollow bicycle crank arm is preferably a one-piece, unitary member that is produced by a tube hydroforming method. The hollow bicycle crank arm has a crank axle attachment part located within the crank axle mounting end portion and a pedal spindle attachment part located within the pedal mounting end portion. The mounting end portions have a crank axle hole and a pedal spindle hole, respectively, with outside diameters that are smaller than the attachment parts, respectively.
    Type: Application
    Filed: March 24, 2005
    Publication date: October 6, 2005
    Applicant: Shimano Inc.
    Inventors: Mitsutoshi Uchida, Masaaki Hara, Toru Iwai
  • Publication number: 20050105444
    Abstract: An apparatus for recording information, which comprises a one-dimensional diode array (21) constituted with a plurality of laser diodes arranged in a line, a modulation control signal generator (23) for supplying the laser diodes constituting the one-dimensional diode array with modulation control signals based on information to be recorded, and an optical system (24) for causing laser light beams obtained from the one-dimensional diode array to be incident upon an optical tape (26), wherein said optical system is operative to focus the laser light beams which have been modulated in response to the modulation control signals and obtained from the one-dimensional diode array so that geometric optical images of the modulated light beams are reduced over the diffraction limit thereof on the optical tape.
    Type: Application
    Filed: July 14, 2003
    Publication date: May 19, 2005
    Inventors: Yujiro Ito, Masaaki Hara, Jun Sawai, Tsunenori Shiimoto, Nobuchika Momochi, Tadaaki Yoshinaka, Takashi Shimizu
  • Publication number: 20050047203
    Abstract: A semiconductor storage device has an array of memories, which store data and which are arranged in a matrix, and can read the data in response to address designation. The semiconductor storage device includes word line pairs, bit line pairs, and resistance portions. The resistance portions are each connected across two word lines of the corresponding word line pair and two bit lines of the corresponding bit line at the corresponding intersection thereof. Each resistance portion includes resistors having differential values in both the word line direction and the bit line direction. This arrangement allows the semiconductor storage device to read data with accuracy at high speed and allows the semiconductor storage device to be miniaturized at low cost.
    Type: Application
    Filed: August 10, 2004
    Publication date: March 3, 2005
    Applicant: Sony Corporation
    Inventors: Tsunenori Shiimoto, Masaaki Hara
  • Publication number: 20040233820
    Abstract: An apparatus for driving a tape-shaped optical recording medium, which comprises a supply reel (41) for supplying an optical tape (40), a take-up reel (42) for taking-up the optical tape (40), a friction capstan (43) for driving the optical tape (40) to run to the take-up reel (42) from the supply reel (41) and a running guide member (46) for guiding the optical tape (40) running between the supply reel (41) and the take-up reel (42). The running guide member (46) has a flat portion forming a guide face portion (70) for facing to the optical tape (40) is operative to cause the optical tape (40) to run along the flat portion. Thereby, an area on the guide face portion (70) of the running guide member (46) where an incident position on the optical tape (40) of a light beam is fixed invariably can be stably maintained to be relatively wide.
    Type: Application
    Filed: March 15, 2004
    Publication date: November 25, 2004
    Inventors: Masaaki Hara, Jun Sawai, Yujiro Ito
  • Publication number: 20040184313
    Abstract: A nonvolatile magnetic memory device having a nonvolatile magnetic memory array comprising write-in word line(s), bit lines and tunnel magnetoresistance devices, wherein when data is written into the tunnel magnetoresistance device, a current I(m)RWL is passed through the m-th-place write-in word line, a current g(0)·I(n)BL is passed through the n-th-place bit line, and at the same time, a current g(k)·I(n)BL is passed through the q-th-place bit line (q=n+k, k is ±1, ±2, . . . , and the total number of the lines is K), and a spatial FIR filter assuming magnetic fields, which are supposed to be formed in the n-th-place bit line and the bit lines that are K in number by the current I(n)BL, to be discrete pulse response and assuming the coefficients g(0) and g(k) to be tap-gains is constituted of the n-th-place bit line and the bit lines that are K in number.
    Type: Application
    Filed: January 30, 2004
    Publication date: September 23, 2004
    Inventors: Masaaki Hara, Tsunenori Shiimoto, Yujiro Ito, Jun Sawai