Abstract: A semiconductor device of an embodiment includes a semiconductor layer, a first insulating film provided on the semiconductor layer, a first electrode film provided on the first insulating film, a second electrode film provided on the first electrode film, and a first field plate electrode provided on the second electrode film. A lower end of the first field plate electrode is located on a second surface of the first electrode film, the second surface being in contact with the second electrode film, rather than a first surface of the first electrode film, the first surface being in contact with the first insulating film.

Abstract: A semiconductor device includes a nitride semiconductor element, a first diode, and a second diode; the nitride semiconductor element includes a conductive mounting bed, a semiconductor substrate formed on the mounting bed, a first nitride semiconductor layer, a second nitride semiconductor layer, a first major electrode, a second major electrode, a first gate electrode, and a second gate electrode; the first diode includes a first anode electrode electrically connected to the mounting bed, and a first cathode electrode electrically connected to the first major electrode; and the second diode includes a second anode electrode electrically connected to the mounting bed, and a second cathode electrode electrically connected to the second major electrode.

Abstract: A semiconductor device includes a first transistor, a first drive circuit including a second transistor, and a second drive circuit including a third transistor. The second transistor and the third transistor are connected in series; and a connection node of the second and third transistors is connected to a gate electrode of the first transistor. The first transistor, the second transistor, and the third transistor are normally-off MOS HEMTs formed in a first substrate that includes GaN. The first drive circuit charges a parasitic capacitance of the first transistor. The second drive circuit discharges the parasitic capacitance of the first transistor.

Abstract: A charging system for a rechargeable battery with a rapid charge capacity. This invention relates to the charging system for the rechargeable battery with a rapid charge capacity which can be recharged at a public place. The charging system comprises a charging equipment for the rapid charge battery, a measurement display unit which measures and displays a charging condition and deterioration of the rapid charge battery, and a fee collection device which collects a charging fee.

Abstract: The substrate for microarray of the present invention comprises a sample fixing part having a vessel-like shape having at least a planar bottom part on which a biological sample is fixed at a plurality of spots and a wall part which rises from a periphery of the bottom part and a supporting part that supports the sample fixing part at a predetermined height to make the bottom part horizontal. According to the present invention, a substrate for microarray that can make to perform a series of operations related to detection of a biological substance by using a microarray easy, provides accurate detection results at the detection, and can be applied to automation of a series of operation relating to the detection of a biological substance can be provided.

Abstract: A composite yarn and a method of manufacturing it are disclosed which makes it possible to produce a fine spun twisted union yarn (33) with natural grandrelle-like patterns. In particular, a manufacturing method of a fine spun twisted union yarn (33) is disclosed where the feed rate or feeding time of one of two fiber bundles (321, 322) is varied according to a 1/f fluctuation, and the one fiber bundle is spun and twisted with the other fiber bundle, thereby the one fiber bundle appears and disappears alternately on the periphery of the spun twisted union yarn (33.).

Abstract: A plating liquid for forming a nickel plating layer containing a dispersed substance and phosphorus having 1.0 g/l or more of sodium is desirably utilized in the high speed plating process. Other important aspects of the invention include a plating method using the aforementioned plating liquid, characterized in that a voltage is impressed while permitting the plating liquid to flow between a surface to be plated of a workpiece at a plating liquid flow rate of 1.0-3.0 m/sec and an electric current density of 20-200 A/dm.sup.2, and an engine cylinder having a plated interior surface characterized in that the plating layer of the cylinder is formed by a high speed plating treatment using the aforementioned plating liquid.

Abstract: An improved surface treatment system, assembly, workstation, method, and liquid for plating and the like. The assembly includes a member defining a fluid passage within the interior surface of a workpiece which is connected to a treating liquid feed channel and a treating liquid discharge channel. Desirably, the assembly includes a sealing mechanism at least partially insertable into the opening of the sealing mechanism to avoid leakage.

Abstract: An improved surface treatment system, assembly, workstation and method for plating and the like. The assembly includes a suction pump along the treating liquid discharge end to circulate treatment fluid and avoid leakage. The assembly includes a member defining a fluid passage within the interior surface of a workpiece which is connected to a treating liquid feed channel and a treating liquid discharge channel. Advantageously, a washing fluid inlet is provided to permit a workpiece to be both treated and washed at the same workstation. The assembly may be used with a cover as an additional means to avoid leakage.

Abstract: A CCD imager includes a large number of light receiving sections each having in turn a semiconductor surface region of a second conductivity type, a first semiconductor region of a first conductivity type, a semiconductor region of the second conductivity type and a second semiconductor region of the first conductivity type, vertically. The second semiconductor region is formed by a dual structure of the low concentration semiconductor region and the high concentration semiconductor region. The dual structure provides for shuttering at a lower voltage since the potential barrier along the depth of the light receiving section is no longer affected by the amount of the stored charges, while spreading of the depletion layer at the junction is suppressed by the high concentration semiconductor region.