Patents by Inventor Masaaki Iwanaga

Masaaki Iwanaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9900569
    Abstract: This projection-type image display device is provided with: a lamp drive unit that drives a lamp; a lamp voltage detection unit that detects a lamp interelectrode voltage (hereinafter referred to as a lamp voltage); an image correction unit that corrects image qualities of image signals to be supplied to an image display element; and a control unit that controls a correction quantity of the image correction unit on the basis of the lamp voltage detected by means of the lamp voltage detection unit. Consequently, deterioration of visibility of a projection image can be suitably suppressed.
    Type: Grant
    Filed: July 4, 2014
    Date of Patent: February 20, 2018
    Assignee: HITACHI MAXELL, LTD.
    Inventors: Eriko Nagata, Shinji Onodera, Satomi Morishita, Naoya Oka, Masaaki Iwanaga
  • Publication number: 20170155880
    Abstract: This projection-type image display device is provided with: a lamp drive unit that drives a lamp; a lamp voltage detection unit that detects a lamp interelectrode voltage (hereinafter referred to as a lamp voltage); an image correction unit that corrects image qualities of image signals to be supplied to an image display element; and a control unit that controls a correction quantity of the image correction unit on the basis of the lamp voltage detected by means of the lamp voltage detection unit. Consequently, deterioration of visibility of a projection image can be suitably suppressed.
    Type: Application
    Filed: July 4, 2014
    Publication date: June 1, 2017
    Inventors: Eriko NAGATA, Shinji ONODERA, Satomi MORISHITA, Naoya OKA, Masaaki IWANAGA
  • Patent number: 8312502
    Abstract: A recording system includes: a receiving apparatus that receives a content; and a recording apparatus that records the content received by the receiving apparatus. The receiving apparatus includes reception means for receiving the content, acceptance means for accepting a user's operation instructing to record the received content, generation means for generating a control signal for controlling a recording operation of the recording apparatus according to the accepted operation, and supply means for supplying the received content and the generated control signal to the recording apparatus, and the recording apparatus includes acquisition means for acquiring the content and the control signal supplied from the receiving apparatus, recording means for recording the acquired content, and control means for controlling the recording means according to the acquired control signal.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: November 13, 2012
    Assignee: Sony Corporation
    Inventor: Masaaki Iwanaga
  • Publication number: 20080288997
    Abstract: A recording system includes: a receiving apparatus that receives a content; and a recording apparatus that records the content received by the receiving apparatus. The receiving apparatus includes reception means for receiving the content, acceptance means for accepting a user's operation instructing to record the received content, generation means for generating a control signal for controlling a recording operation of the recording apparatus according to the accepted operation, and supply means for supplying the received content and the generated control signal to the recording apparatus, and the recording apparatus includes acquisition means for acquiring the content and the control signal supplied from the receiving apparatus, recording means for recording the acquired content, and control means for controlling the recording means according to the acquired control signal.
    Type: Application
    Filed: May 13, 2008
    Publication date: November 20, 2008
    Inventor: Masaaki IWANAGA
  • Patent number: 6917388
    Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: July 12, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Kazutaka Naka, Atsushi Maruyama, Hiroyuki Urata, Masaaki Iwanaga
  • Patent number: 6707503
    Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: March 16, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kazutaka Naka, Atsushi Maruyama, Hiroyuki Urata, Masaaki Iwanaga
  • Publication number: 20020093592
    Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an AID converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of White-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.
    Type: Application
    Filed: February 11, 2002
    Publication date: July 18, 2002
    Inventors: Kazutaka Naka, Atsushi Maruyama, Hiroyuki Urata, Masaaki Iwanaga
  • Patent number: 5990968
    Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.
    Type: Grant
    Filed: July 25, 1996
    Date of Patent: November 23, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Kazutaka Naka, Atsushi Maruyama, Hiroyuki Urata, Masaaki Iwanaga
  • Patent number: 5541665
    Abstract: In order to enable sampling of high definition still video signals in addition to common video signals, a function is added for sampling video signals with every other plurality of picture elements as an interval to an image processing apparatus without using a sampling circuit which requires high speed operations. The invention is also intended to change over between two circuits that is, a circuit for using a picture element clock regenerated by a PLL circuit as a sampling clock for analog to digital converters and a circuit for using a clock obtained by dividing the picture element clock as a sampling clock for the analog to digital converters to sample video signals with every other plurality of picture elements as an interval. Thus, it is possible to carry out sampling of high definition video signals with high frequencies in addition to common video signals without necessity of raising the operating speed of the sampling circuit.
    Type: Grant
    Filed: December 22, 1994
    Date of Patent: July 30, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Urata, Masahiro Eto, Atsushi Maruyama, Fumio Inoue, Masanori Ogino, Kiyoshi Yamamoto, Kazutaka Naka, Masaaki Iwanaga