Abstract: A power circuit includes a reference potential circuit, a step-up circuit, and a conversion circuit. The reference potential circuit generates a reference potential. The step-up circuit generates a desired internal potential by stepping up a power supply potential. The step-up circuit includes a comparison circuit, a differential amplifier circuit, and a switch element. The comparison circuit outputs the result of comparison between a potential and the reference potential. The differential amplifier circuit is turned on or off by the operation control signal. The switch element performs on/off control according to the operation control signal and resets the output potential of the differential amplifier circuit. The conversion circuit converts the of the operation control signal so as to make longer the on period of the differential amplifier circuit and the off period of switch element.

Abstract: According to one embodiment, provided is a semiconductor boost circuit including a pump circuit, a switch signal generating circuit and a clock signal generating circuit. The pump circuit receives a clock signal and performs charge pump operation on the basis of the clock signal to boost an input potential to a set potential. The switch signal generating circuit outputs CLK cycle switch signal when a potential output by the pump circuit reaches a first potential greater than the input potential and less than the set potential. The clock signal generating circuit outputs the clock signal having a first frequency if not receiving the CLK cycle switch signal, and, on the other hand, outputs the clock signal having a second frequency greater than the first frequency if receiving the CLK cycle switch signal.

Abstract: A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.

Abstract: A power circuit includes a reference potential circuit, a step-up circuit, and a conversion circuit. The reference potential circuit generates a reference potential. The step-up circuit generates a desired internal potential by stepping up a power supply potential. The step-up circuit includes a comparison circuit, a differential amplifier circuit, and a switch element. The comparison circuit outputs the result of comparison between a potential and the reference potential. The differential amplifier circuit is turned on or off by the operation control signal. The switch element performs on/off control according to the operation control signal and resets the output potential of the differential amplifier circuit. The conversion circuit converts the of the operation control signal so as to make longer the on period of the differential amplifier circuit and the off period of switch element.

Abstract: A voltage generation circuit includes a pump circuit, a first unit, a first switch, and a first capacitor. The pump circuit generates a first voltage and outputs the first voltage to a first node. The first unit includes a first resistance unit to output a second voltage at a second node. The first switch connects the second node and an output terminal. A resistance value of a parasitic resistance formed in an interconnection from the second node to the output terminal is smaller than a resistance value of the first resistance unit. The first capacitor includes one of electrodes and the other electrodes. The one of electrodes is connected to an interconnection connecting the second node and the first switch element. The other of the electrodes is grounded. A capacitance of the first capacitor element is larger than a capacitance connected to the output terminal.

Abstract: A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.

Abstract: A dynamic random access memory (DRAM) has a refresh-control function under control by an internal refresh-control signal. The DRAM includes: a cell array having a plurality of DRAM cells divided into a plurality of blocks, the DRAM cells being driven through word lines for data transfer with bit lines; a decoder to select word lines and bit lines connected to the cell array; a sense amplifier to amplify data on the bit lines; and a refresh controller to limit refresh to the cell array so that at least one externally-accessed block cell among the blocks is refreshed.

Abstract: A dynamic random access memory (DRAM) has a refresh-control function under control by an internal refresh-control signal. The DRAM includes: a cell array having a plurality of DRAM cells divided into a plurality of blocks, the DRAM cells being driven through word lines for data transfer with bit lines; a decoder to select word lines and bit lines connected to the cell array; a sense amplifier to amplify data on the bit lines; and a refresh controller to limit refresh to the cell array so that at least one externally-accessed block cell among the blocks is refreshed.

Abstract: A semiconductor integrated circuit includes a bias voltage regulation circuit having variable resistors which are provided between voltage output circuits of higher and lower potential sides and changes corresponding to a specified condition such as V.sub.CC and a temperature. The variable resistors and bias voltage output circuits form a V.sub.CC divider, and the variable resistors properly regulate a bias voltage supplied to an oscillation circuit corresponding to each of the specified conditions. Accordingly, if the oscillation circuit is used in an automatic refresh circuit of a PSRAM, an increase of a refresh operation frequency is suppressed regardless of an increase in V.sub.CC. Since a temperature depending variable resistor causes a resistance value to be reduced by the predetermined characteristics against the temperature increase, it is possible to set an oscillation frequency to provide a desired pause for guarantee of circuit operation.

Abstract: In the memory cell provided with spare cells and normal cells, the time required to discriminate the spare column address from the normal column address or vice versa can be reduced, and thereby a high speed memory access can be realized. When an address is given from the counter to a memory circuit having the spare address and the normal address, before the counter outputs an address to the memory circuit, the spare/normal discriminating circuit acquires previously the address outputted from the counter and discriminates whether the address is the spare address or the normal address. On the basis of this discrimination, the select circuits switch the address to be applied from the select circuits to the memory circuit from the normal address to the spare address or vice versa.