Abstract: In a vertical MOSFET having a trench gate structure, a lifetime killer region is provided in a p-type epitaxial layer formed by epitaxial growth. The lifetime killer region includes an electron lifetime killer that causes electrons entering the lifetime killer region to recombine and become extinct. As a result, the lifetime killer region decreases the electrons generated at the pn interface of the p-type epitaxial layer and an n-type drift layer and enables a configuration in which electrons are not delivered to the p-type epitaxial layer.

Abstract: In a vertical MOSFET having a trench gate structure, a lifetime killer region is provided in a p-type epitaxial layer formed by epitaxial growth. The lifetime killer region includes an electron lifetime killer that causes electrons entering the lifetime killer region to recombine and become extinct. As a result, the lifetime killer region decreases the electrons generated at the pn interface of the p-type epitaxial layer and an n-type drift layer and enables a configuration in which electrons are not delivered to the p-type epitaxial layer.

Abstract: A method for preparing data for exposure includes forming a first plurality of rectangular patterns from a reticle preparing rule; lining an object pattern for performing reticle exposure with the first rectangular patterns, and extracting a second plurality of rectangular patterns, disposed in an N×N matrix, from the first plurality of rectangular patterns in the object pattern; and performing a violation detecting treatment and a correcting treatment of the pattern width and the pattern distance of the reticle exposure pattern on the basis of the distance between the second plurality of rectangular patterns.

Abstract: A method for preparing data for exposure includes forming a first plurality of rectangular patterns from a reticle preparing rule; lining an object pattern for performing reticle exposure with the first rectangular patterns, and extracting a second plurality of rectangular patterns, disposed in an N×N matrix, from the first plurality of rectangular patterns in the object pattern; and performing a violation detecting treatment and a correcting treatment of the pattern width and the pattern distance of the reticle exposure pattern on the basis of the distance between the second plurality of rectangular patterns.

Abstract: A variable rectangle-type electron beam exposure apparatus for forming rectangular beams of different angles which is capable of highly finely conducting exposure with respect to a predetermined fine line pattern having an arbitrary angle in the pattern region.

Abstract: A variable rectangle-type electron beam exposure apparatus for forming rectangular beams of different angles which is capable of highly finely conducting exposure with respect to a predetermined fine line pattern having an arbitrary angle in the pattern region.

Abstract: A variable rectangle-type electron beam exposure apparatus for forming rectangular beams of different angles is provided which is capable of highly finely conducting exposure with respect to a predetermined fine line pattern having an arbitrary angle in the pattern region.

Abstract: A computer implemented method and an apparatus for generating exposure data of a layout pattern used to fabricate semiconductor integrated circuits. The layout pattern is first analyzed to determine if it can be modified to one or more predefined patterns without having to segment the layout pattern into rectangular patterns. The layout pattern is then modified to the one or more predefined patterns. The modified pattern is also analyzed to determine if it can be modified into segmental block patterns and if so, it is modified accordingly. Finally, exposure data is generated using the modified segmental block patterns.

Abstract: Producing an exposure data used for exposing a design pattern data of a semiconductor integrated circuit on an exposure medium. Repetitive exposure pattern data is extracted from the design pattern data as a group of exposure pattern data. The group of exposure pattern data includes plural pieces of the repetitive exposure pattern data. A rearrangement information table, which includes information for placing the plural pieces of repetitive exposure pattern data in a predetermined rearrangement area, is generated. The design pattern data is rearranged based on the rearrangement information table to generate the exposure data.

Abstract: Improved block exposure techniques for a semiconductor wafer that use a block mask with an exposure pattern separated into blocks are disclosed. Each block comprises a plurality of block elements having parts of the exposure pattern and installed on the block mask. A plurality of block elements having predetermined patterns are extracted from the exposure pattern. Each of the predetermined patterns is present in at least one partial area of an associated one of the block elements. A combination of a plurality of extracted block elements having patterns arrangeable in a single block is specified based on pattern present areas of the individual extracted block elements. The patterns of combined extracted block elements are laid out in a single block and an irradiation mode of that block is changed from a full irradiation mode to a partial irradiation mode.

Abstract: A mask and a block exposure method for transferring a plurality of patterns of the same shape onto an exposure medium while forming the cross-sectional shape of a beam emitted from a light source into a desired pattern. The mask has at least one basic pattern formed by extracting portions of a common shape from pattern information to be exposed. A plurality of blocks are arranged on the mask. Each block includes a plurality of the basic patterns.

Abstract: A method of dividing a block pattern for use in a block exposure, to be implemented on a computer, divides an arbitrary block which is to be formed in a block mask that is used for the block exposure when the arbitrary block is judged as including a prohibiting pattern which is undesirable from a point of view of the block exposure.

Abstract: A pattern data processing method processes hierarchical pattern data which has a hierarchical structure and describes in each level thereof one or a plurality of internal cells constituting one or a plurality of logic blocks of a semiconductor integrated circuit device which is to be produced. The pattern processing method comprises the steps of defining a frame at a boundary between a level i of the hierarchical structure and a level i+1 which is higher than the level i, cutting a first portion of a pattern which protrudes out of the frame form the level i to the level i+1 and defining the cut, first portion as a pattern of the level i+1, cutting a second portion of a pattern which protrudes out of the frame from the level i+1 to the level i and deleting the cut, second portion, and repeating the steps of cutting the first and second portions for a predetermined number of levels for increasing values of i, where i=1, 2, . . .