Patents by Inventor Masaaki Ogino

Masaaki Ogino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10658183
    Abstract: An impurity-doping apparatus is provided with: a supporting plate which supports a semiconductor substrate; a wall-like block disposed above the supporting plate floating away from the semiconductor substrate, the wall-like block implements a recess inside so as to establish a space for a solution region containing impurity elements, the solution region is localized on an upper surface of the semiconductor substrate, the upper surface being opposite to an bottom surface facing to the supporting plate; and a laser optical system, configured to irradiate a laser beam onto the upper surface of the semiconductor substrate, through the solution region surrounded by the wall-like block, wherein the impurity elements are doped into a part of the semiconductor substrate by irradiation of the laser beam.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: May 19, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi Iguchi, Haruo Nakazawa, Masaaki Ogino
  • Patent number: 10355089
    Abstract: A MOS gate structure including a p base region, a p epitaxial layer, an n++ source region, a p+ contact region, an n inversion region, a gate insulating film, and a gate electrode and a front surface electrode are provided on the front surface of an epitaxial substrate obtained by depositing an n? epitaxial layer on the front surface of a SiC substrate. A first metal film is provided on the front surface electrode so as to cover 10% or more, preferably, 60% to 90%, of an entire upper surface of the front surface electrode. The SiC-MOSFET is manufactured by forming a rear surface electrode, forming the first metal film on the surface of the front surface electrode, and annealing in a N2 atmosphere. According to this structure, it is possible to suppress a reduction in gate threshold voltage in a semiconductor device using a SiC semiconductor.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 16, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Saito, Masaaki Ogino, Eiji Mochizuki, Yoshikazu Takahashi
  • Patent number: 10115587
    Abstract: A reverse blocking IGBT is manufactured using a silicon wafer sliced from a single crystal silicon ingot which is manufactured by a floating method using a single crystal silicon ingot manufactured by a Czochralski method as a raw material. A separation layer for ensuring a reverse blocking performance of the reverse blocking IGBT is formed by diffusing impurities implanted into the silicon wafer using a thermal diffusion process. The thermal diffusion process for forming the separation layer is performed in an inert gas atmosphere at a temperature equal to or more than 1290° C. and less than the melting point of silicon. In this way, no crystal defect occurs in the silicon wafer and it is possible to prevent the occurrence of a reverse breakdown voltage defect or a forward defect in the reverse blocking IGBT and thus improve the yield of a semiconductor element.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: October 30, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Hidenao Kuribayashi, Hideaki Teranishi
  • Patent number: 9972499
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a front surface and a back surface; forming a transition metal layer on a surface of the semiconductor substrate; and exposing the semiconductor substrate having the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves, to cause the transition metal layer to generate heat. During exposure of the semiconductor substrate, a portion of the semiconductor substrate contacting the transition metal layer is heated by a transfer of heat from the transition metal layer and, at an interface of the transition metal layer and the semiconductor substrate, an ohmic contact is formed by reaction of the transition metal layer and the semiconductor substrate, such as to form a transition metal silicide when the semiconductor substrate is silicon carbide. The ohmic contact provides a lower contact resistivity and device properties can be prevented from degrading.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: May 15, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Tsunehiro Nakajima, Kenichi Iguchi, Masaaki Tachioka, Kiyokazu Nakagawa
  • Patent number: 9905684
    Abstract: A semiconductor device includes a semiconductor substrate that is made of a semiconductor material with a wider band gap than silicon, a field effect transistor, including a front surface element structure, provided on a front surface of the substrate, and a drain electrode having surface contact with the substrate so as to form a Schottky junction between the semiconductor substrate and the drain electrode.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: February 27, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Tsunehiro Nakajima
  • Patent number: 9892919
    Abstract: A first nickel film is deposited inside a contact hole of an interlayer dielectric formed on an n+-type SiC substrate. Irradiation with a first laser is carried out, forming an Ohmic contact with a silicon carbide semiconductor. A second nickel film and a front surface electrode film are deposited on the first nickel film, forming a source electrode. The back surface of the n+-type SiC substrate is ground, and a third nickel film is formed on the ground back surface of the n+-type SiC substrate. Irradiation with a second laser is carried out, forming an Ohmic contact with the silicon carbide semiconductor. A fourth nickel film and a back surface electrode film are deposited on the third nickel film, forming a drain electrode. By so doing, it is possible to prevent electrical characteristic deterioration of a semiconductor device, and to prevent warping and cracking of a wafer.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: February 13, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Tachioka, Naoto Fujishima, Masaaki Ogino, Tsunehiro Nakajima, Kenichi Iguchi
  • Patent number: 9666676
    Abstract: A method for manufacturing a semiconductor device having a MOS gate structure includes forming a device structure on a semiconductor substrate; forming an interlayer dielectric to cover the device structure; forming a contact hole through the interlayer dielectric; forming a transition metal film (e.g., Ni) on a portion of the semiconductor substrate exposed by the contact hole; (e) forming a metal film (e.g., Ti) on the entire surface of the semiconductor substrate; forming an oxide film in the surface of the metal film; selectively removing the metal film in which the oxide film has been formed, to thereby expose the transition metal film; and (h) exposing, to a hydrogen plasma atmosphere, the semiconductor substrate in which the transition metal film and the oxide film have been exposed, to thereby cause the transition metal film to generate heat and react with the semiconductor substrate and form an ohmic contact there between.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: May 30, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaaki Ogino
  • Patent number: 9659774
    Abstract: A method for introducing impurity into a semiconductor substrate includes bringing a solution containing a compound of an impurity element into contact with a primary surface of a semiconductor substrate; and irradiating the primary surface of the semiconductor substrate with a laser beam through the solution to raise a temperature of the primary surface of the semiconductor substrate at a position irradiated by the laser beam so as to dope the impurity element into the semiconductor substrate. The laser beam irradiation is performed such that the raised temperature does not return to room temperature until a prescribed dose of the impurity element is caused to be doped into the semiconductor substrate.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 23, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Kenichi Iguchi, Masaaki Ogino
  • Patent number: 9564334
    Abstract: A method of manufacturing a semiconductor device includes forming a device structure in a surface of a semiconductor substrate, forming, in a face of the semiconductor substrate, a transition metal layer that contacts the semiconductor substrate, and exposing the semiconductor substrate having the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves to cause the transition metal layer to generate heat. During exposure of the semiconductor substrate to the hydrogen plasma atmosphere, a portion of the semiconductor substrate contacting the transition metal layer is heated by a transfer of the heat from the transition metal layer, and an ohmic contact is formed at an interface of the transition metal layer and the semiconductor substrate by reaction of the transition metal layer and the semiconductor substrate. When the semiconductor substrate is silicon carbide, the ohmic contact is composed of a silicide, such as a transition metal silicide.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: February 7, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi Iguchi, Haruo Nakazawa, Tsunehiro Nakajima, Masaaki Ogino, Masaaki Tachioka
  • Patent number: 9548205
    Abstract: A method of manufacturing a semiconductor device that reduces degradation of device properties includes forming an impurity region in a surface layer of a semiconductor substrate by ion injection; forming a transition metal layer in a surface of the impurity region; and exposing the semiconductor substrate with the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves. The transition metal layer is heated and the heat is transferred from the transition metal layer to the impurity region to form an ohmic contact at the interface of the transition metal layer and the impurity region by reaction of the transition metal layer and the impurity region, and the impurity region is activated. When the substrate is a silicon carbide substrate, the ohmic contact is composed of a transition metal silicide and the impurity region, which is an ion injection layer, is activated.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: January 17, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Tsunehiro Nakajima, Kenichi Iguchi, Masaaki Tachioka
  • Publication number: 20160284547
    Abstract: An impurity-doping apparatus is provided with: a supporting plate which supports a semiconductor substrate; a wall-like block disposed above the supporting plate floating away from the semiconductor substrate, the wall-like block implements a recess inside so as to establish a space for a solution region containing impurity elements, the solution region is localized on an upper surface of the semiconductor substrate, the upper surface being opposite to an bottom surface facing to the supporting plate; and a laser optical system, configured to irradiate a laser beam onto the upper surface of the semiconductor substrate, through the solution region surrounded by the wall-like block, wherein the impurity elements are doped into a part of the semiconductor substrate by irradiation of the laser beam.
    Type: Application
    Filed: June 6, 2016
    Publication date: September 29, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi IGUCHI, Haruo NAKAZAWA, Masaaki OGINO
  • Patent number: 9450070
    Abstract: A method for manufacturing a silicon semiconductor substrate including a diffusion layer prior to forming a semiconductor device thereon, includes providing a silicon semiconductor substrate which is manufactured by a floating zone method; and performing thermal diffusion at a heat treatment temperature that is equal to or higher than 1290° C. and that is lower than a melting temperature of a silicon crystal to form a diffusion layer with a depth of 50 ?m or more in the silicon semiconductor substrate, the thermal diffusion including a first heat treatment performed in an atmosphere consisting of oxygen or oxygen and at least one of argon, helium, or neon, followed by a second heat treatment performed in an atmosphere comprised of nitrogen or nitrogen and oxygen to form the diffusion layer. The method suppresses the occurrence of crystal defects, reduces the amount of inert gas used, and reduces manufacturing costs.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: September 20, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hideaki Teranishi, Haruo Nakazawa, Masaaki Ogino
  • Patent number: 9431270
    Abstract: A method for producing a semiconductor device is disclosed which includes a diffusion step of forming, on a CZ-FZ silicon semiconductor substrate, a deep diffusion layer involving a high-temperature and long-term thermal diffusion process which is performed at a thermal diffusion temperature of 1290° C. to a melting temperature of a silicon crystal for 100 hours or more; and a giving step of giving a diffusion source for an interstitial silicon atom to surface layers of two main surfaces of the silicon semiconductor substrate before the high-temperature, long-term thermal diffusion process. The step of giving the diffusion source for the interstitial silicon atom to the surface layers of the two main surfaces of the silicon semiconductor substrate is performed by forming thermally-oxidized films on two main surfaces of the silicon semiconductor substrate or by implanting silicon ions into surface layers of the two main surfaces of the silicon semiconductor substrate.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: August 30, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Hidenao Kuribayashi, Hideaki Teranishi
  • Publication number: 20160189968
    Abstract: A method of manufacturing a semiconductor device that reduces degradation of device properties includes forming an impurity region in a surface layer of a semiconductor substrate by ion injection; forming a transition metal layer in a surface of the impurity region; and exposing the semiconductor substrate with the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves. The transition metal layer is heated and the heat is transferred from the transition metal layer to the impurity region to form an ohmic contact at the interface of the transition metal layer and the impurity region by reaction of the transition metal layer and the impurity region, and the impurity region is activated. When the substrate is a silicon carbide substrate, the ohmic contact is composed of a transition metal silicide and the impurity region, which is an ion injection layer, is activated.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 30, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo NAKAZAWA, Masaaki OGINO, Tsunehiro NAKAJIMA, Kenichi IGUCHI, Masaaki TACHIOKA
  • Publication number: 20160189967
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a front surface and a back surface; forming a transition metal layer in a surface of the semiconductor substrate; and exposing the semiconductor substrate having the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves, to cause the transition metal layer to generate heat, Thus, during the exposure of the semiconductor substrate, a portion of the semiconductor substrate contacting the transition metal layer is heated by a transfer of heat from the transition metal layer and, at an interface of the transition metal layer and the semiconductor substrate, an ohmic contact is formed by reaction of the transition metal layer and the semiconductor substrate, such as to form a transition metal silicide when the semiconductor substrate is silicon carbide. The ohmic contact provides a lower contact resistivity and device properties can be prevented from degrading.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 30, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo NAKAZAWA, Masaaki OGINO, Tsunehiro NAKAJIMA, Kenichi IGUCHI, Masaaki TACHIOKA, Kiyokazu NAKAGAWA
  • Publication number: 20160189969
    Abstract: A method of manufacturing a semiconductor device includes forming a device structure in a surface of a semiconductor substrate, forming, in a face of the semiconductor substrate, a transition metal layer that contacts the semiconductor substrate, and exposing the semiconductor substrate having the transition metal layer formed thereon to a hydrogen plasma atmosphere formed by microwaves to cause the transition metal layer to generate heat. During exposure of the semiconductor substrate to the hydrogen plasma atmosphere, a portion of the semiconductor substrate contacting the transition metal layer is heated by a transfer of the heat from the transition metal layer, and an ohmic contact is formed at an interface of the transition metal layer and the semiconductor substrate by reaction of the transition metal layer and the semiconductor substrate. When the semiconductor substrate is silicon carbide, the ohmic contact is composed of a silicide, such as a transition metal silicide.
    Type: Application
    Filed: March 9, 2016
    Publication date: June 30, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Kenichi IGUCHI, Haruo NAKAZAWA, Tsunehiro NAKAJIMA, Masaaki OGINO, Masaaki TACHIOKA
  • Patent number: 9355858
    Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 31, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki Wakimoto, Kenichi Iguchi, Koh Yoshikawa, Tsunehiro Nakajima, Shunsuke Tanaka, Masaaki Ogino
  • Publication number: 20160126319
    Abstract: A method for manufacturing a semiconductor device having a MOS gate structure includes forming a device structure on a semiconductor substrate; forming an interlayer dielectric to cover the device structure; forming a contact hole through the interlayer dielectric; forming a transition metal film (e.g., Ni) on a portion of the semiconductor substrate exposed by the contact hole; (e) forming a metal film (e.g., Ti) on the entire surface of the semiconductor substrate; forming an oxide film in the surface of the metal film; selectively removing the metal film in which the oxide film has been formed, to thereby expose the transition metal film; and (h) exposing, to a hydrogen plasma atmosphere, the semiconductor substrate in which the transition metal film and the oxide film have been exposed, to thereby cause the transition metal film to generate heat and react with the semiconductor substrate and form an ohmic contact there between.
    Type: Application
    Filed: October 13, 2015
    Publication date: May 5, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Masaaki OGINO
  • Patent number: 9240456
    Abstract: A method includes forming on a first main surface of a semiconductor wafer of a first conduction type, a gate electrode of a semiconductor element, an edge termination region for forming a breakdown voltage of the semiconductor element, and a first semiconductor region of a second conduction type which surrounds the semiconductor element and the edge termination region. A groove may be formed to reach the first semiconductor region from a second main surface of the semiconductor wafer. The groove is formed so that a portion of the semiconductor wafer, that forms an outer circumferential end of the semiconductor wafer, remains and the groove is further towards a center of the semiconductor wafer than the outer circumferential end. A third semiconductor region of the second conduction type is on a side wall of the groove and electrically connects the first semiconductor region and a second semiconductor region.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: January 19, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki Wakimoto, Masaaki Ogino
  • Publication number: 20160005606
    Abstract: A method for introducing impurity into a semiconductor substrate includes bringing a solution containing a compound of an impurity element into contact with a primary surface of a semiconductor substrate; and irradiating the primary surface of the semiconductor substrate with a laser beam through the solution to raise a temperature of the primary surface of the semiconductor substrate at a position irradiated by the laser beam so as to dope the impurity element into the semiconductor substrate. The laser beam irradiation is performed such that the raised temperature does not return to room temperature until a prescribed dose of the impurity element is caused to be doped into the semiconductor substrate.
    Type: Application
    Filed: June 3, 2015
    Publication date: January 7, 2016
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Haruo NAKAZAWA, Kenichi IGUCHI, Masaaki OGINO