Patents by Inventor Masafumi Hamaguchi
Masafumi Hamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200027962Abstract: According to one embodiment, a semiconductor device includes a memory cell array including a first memory cell provided on a substrate and a second memory cell provided on the substrate. The memory cell array includes a charge storage layer provided on the substrate and a control electrode provided on the charge storage layer. A coupling ratio of the second memory cell is different from a coupling ratio of the first memory cell.Type: ApplicationFiled: September 30, 2019Publication date: January 23, 2020Inventors: Masafumi HAMAGUCHI, Shinji KAWAHARA
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Patent number: 10366913Abstract: A method for manufacturing a semiconductor element includes forming a first region in a semiconductor region by ion-implanting impurities using a first mask; forming an interconnect including a gate portion extending in a first direction over the first region; and forming a source/drain region by ion-implanting impurities into a second region. A gate threshold voltage of the semiconductor element has first to third correlations dependent respectively on distances between an inner wall of the first mask and an outer edge of the second region, between the gate portion and the outer edge of the second region and between the outer edge of the second portion and a portion of the interconnect other than the gate portion. At least one of the distances is determined based on the first to third correlations to obtain a prescribed gate threshold voltage of the semiconductor element.Type: GrantFiled: September 13, 2016Date of Patent: July 30, 2019Assignee: Kabushiki Kaisha ToshibaInventor: Masafumi Hamaguchi
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Publication number: 20170256555Abstract: According to one embodiment, a semiconductor device includes a memory cell array including a first memory cell provided on a substrate and a second memory cell provided on the substrate. The memory cell array includes a charge storage layer provided on the substrate and a control electrode provided on the charge storage layer. A coupling ratio of the second memory cell is different from a coupling ratio of the first memory cell.Type: ApplicationFiled: December 7, 2016Publication date: September 7, 2017Inventors: Masafumi HAMAGUCHI, Shinji KAWAHARA
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Publication number: 20170256629Abstract: A method for manufacturing a semiconductor element includes forming a first region in a semiconductor region by ion-implanting impurities using a first mask; forming an interconnect including a gate portion extending in a first direction over the first region; and forming a source/drain region by ion-implanting impurities into a second region. A gate threshold voltage of the semiconductor element has first to third correlations dependent respectively on distances between an inner wall of the first mask and an outer edge of the second region, between the gate portion and the outer edge of the second region and between the outer edge of the second portion and a portion of the interconnect other than the gate portion. At least one of the distances is determined based on the first to third correlations to obtain a prescribed gate threshold voltage of the semiconductor element.Type: ApplicationFiled: September 13, 2016Publication date: September 7, 2017Inventor: Masafumi HAMAGUCHI
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Publication number: 20150255552Abstract: A semiconductor device includes a substrate, and a gate electrode formed on the substrate on a gate insulation film. The semiconductor device also includes a source diffusion layer and a drain diffusion layer which are formed on the substrate where the gate electrode is sandwiched between the source diffusion layer and the drain diffusion layer, one or more source contacts formed on the source diffusion layer; and one or more drain contacts formed on the drain diffusion layer. At least one of the source contacts and the drain contacts includes a first contact region having a first size and a second contact region having a second size larger than the first size on the same source diffusion layer or on the same drain diffusion layer.Type: ApplicationFiled: May 20, 2015Publication date: September 10, 2015Inventor: Masafumi HAMAGUCHI
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Patent number: 9064843Abstract: A semiconductor device includes a substrate, and a gate electrode formed on the substrate on a gate insulation film. The semiconductor device also includes a source diffusion layer and a drain diffusion layer which are formed on the substrate where the gate electrode is sandwiched between the source diffusion layer and the drain diffusion layer, one or more source contacts formed on the source diffusion layer; and one or more drain contacts formed on the drain diffusion layer. At least one of the source contacts and the drain contacts includes a first contact region having a first size and a second contact region having a second size larger than the first size on the same source diffusion layer or on the same drain diffusion layer.Type: GrantFiled: June 14, 2013Date of Patent: June 23, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Masafumi Hamaguchi
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Publication number: 20140197485Abstract: A semiconductor device includes a substrate, and a gate electrode formed on the substrate on a gate insulation film. The semiconductor device also includes a source diffusion layer and a drain diffusion layer which are formed on the substrate where the gate electrode is sandwiched between the source diffusion layer and the drain diffusion layer, one or more source contacts formed on the source diffusion layer; and one or more drain contacts formed on the drain diffusion layer. At least one of the source contacts and the drain contacts includes a first contact region having a first size and a second contact region having a second size larger than the first size on the same source diffusion layer or on the same drain diffusion layer.Type: ApplicationFiled: June 14, 2013Publication date: July 17, 2014Inventor: Masafumi HAMAGUCHI
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Patent number: 8598006Abstract: An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized.Type: GrantFiled: March 16, 2010Date of Patent: December 3, 2013Assignees: International Business Machines Corporation, Toshiba America Electronic Components, Inc.Inventors: Joel P. de Souza, Masafumi Hamaguchi, Ahmet S. Ozcan, Devendra K. Sadana, Katherine L. Saenger, Donald R. Wall
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Patent number: 8193616Abstract: A Direct Silicon Bonded substrate can include a first substrate and a second substrate in which the second substrate can be rotated to an azimuthal twist angle of 45 degrees in comparison to the first substrate. Disclosed are a semiconductor device and a method for making a semiconductor device that includes a DSB substrate with an adjusted thickness based upon the threshold voltage (Vt). In other words, a thicker substrate or layer can correspond to a high threshold voltage (HVt) and a thinner substrate or layer can correspond to a low threshold voltage (LVt) in order to improve mobility in LVt devices.Type: GrantFiled: June 29, 2009Date of Patent: June 5, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masafumi Hamaguchi, Ryoji Hasumi
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Publication number: 20120080777Abstract: According to certain embodiments, a semiconductor structure is formed having a gate oxide formed over a semiconductor substrate. The gate oxide is formed as to have three different regions characterized by a different average thickness of gate oxide in each region. A first oxidation process is performed on a semiconductor substrate having both a Si (110) orientation region and a Si (100) orientation region on a surface thereof. Gate oxide is formed at a faster rate on the Si (110) orientation region of the semiconductor substrate relative to the Si (100) orientation region. A portion of the gate oxide is selectively removed and a second oxidation process is performed to form additional gate oxide. A triple oxide semiconductor substrate is recovered with the gate oxide having three different thickness formed thereon. The triple oxide semiconductor substrate is formed using a decreased number of processing acts.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Masafumi Hamaguchi, Ryoji Hasumi
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Publication number: 20110230030Abstract: An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized.Type: ApplicationFiled: March 16, 2010Publication date: September 22, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Joel P. de Souza, Masafumi Hamaguchi, Ahmet S. Ozcan, Devendra K. Sadana, Katherine L. Saenger, Donald R. Wall
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Publication number: 20100327395Abstract: A Direct Silicon Bonded substrate can include a first substrate and a second substrate in which the second substrate can be rotated to an azimuthal twist angle of 45 degrees in comparison to the first substrate. Disclosed are a semiconductor device and a method for making a semiconductor device that includes a DSB substrate with an adjusted thickness based upon the threshold voltage (Vt). In other words, a thicker substrate or layer can correspond to a high threshold voltage (HVt) and a thinner substrate or layer can correspond to a low threshold voltage (LVt) in order to improve mobility in LVt devices.Type: ApplicationFiled: June 29, 2009Publication date: December 30, 2010Applicant: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Masafumi Hamaguchi, Ryoji Hasumi
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Patent number: 7605043Abstract: A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.Type: GrantFiled: July 12, 2007Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Masafumi Hamaguchi
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Publication number: 20090173967Abstract: This invention provides a strained-channel field effect transistor (FET) in which the semiconductor of the channel of the FET is formed in a compliant substrate layer disposed over a twist-bonded semiconductor interface. This FET geometry increases the efficacy of local stress elements such as stress liners and embedded lattice-mismatched source/drain regions by mechanically decoupling the semiconductor of the channel region from the underlying rigid substrate. These strained-channel FETs may be incorporated into complementary metal oxide semiconductor (CMOS) circuits in various combinations. In one embodiment of this invention, both pFETs and nFETs are in a twist-bonded (001) silicon layer on a (001) silicon base layer. In another embodiment, pFETs are in a twist-bonded (011) silicon layer on a (001) silicon base layer and nFETs are in a conventional, non-twist-bonded (001) silicon base layer.Type: ApplicationFiled: January 4, 2008Publication date: July 9, 2009Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.Inventors: Masafumi Hamaguchi, Ryoji Hasumi, Haizhou Yin, Katherine L. Saenger
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Publication number: 20090159939Abstract: A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.Type: ApplicationFiled: February 23, 2009Publication date: June 25, 2009Inventor: Masafumi HAMAGUCHI
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Patent number: 7514763Abstract: A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.Type: GrantFiled: October 30, 2007Date of Patent: April 7, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Masafumi Hamaguchi
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Publication number: 20080176373Abstract: A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.Type: ApplicationFiled: July 12, 2007Publication date: July 24, 2008Inventor: Masafumi Hamaguchi
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Publication number: 20080067633Abstract: A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.Type: ApplicationFiled: October 30, 2007Publication date: March 20, 2008Inventor: Masafumi Hamaguchi
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Patent number: 7271443Abstract: A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.Type: GrantFiled: March 15, 2005Date of Patent: September 18, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Masafumi Hamaguchi
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Publication number: 20060131657Abstract: In a surface region of a semiconductor substrate, an element isolation region for isolating the substrate into a plurality of element regions is formed. In each of the plurality of element regions, a pair of trenches, which are formed apart from each other and each have a bottom surface and side surfaces, are formed. Further, an insulation film is formed on each of the bottom surfaces in the pair of trenches, and on the insulation film, a source region and a drain region are formed so as to embed the inside of the pair of trenches. In addition, a channel region which is interconnected to the semiconductor substrate is formed between the source region and a drain region, and a gate electrode is formed on each channel region.Type: ApplicationFiled: December 8, 2005Publication date: June 22, 2006Inventor: Masafumi Hamaguchi