Abstract: A charge and discharge signal circuit includes: high side transistors connected in series; low side transistors connected in series; high side drive circuits; low side drive circuits; and a drive signal generation circuit, wherein each drive circuit includes: a high side level shifter; a high side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the high side transistor; and a high side drive part, to which an output of the high side level shifter is supplied, and each of the low side drive circuits includes: a low side level shifter; a low side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the low side transistor; and a low side drive part, to which an output of the low side level shifter is supplied.

Abstract: A DC-DC converter includes: a high-side switch; a low-side switch coupled to the high-side switch in series; a capacitor configured to be charged while the low-side switch is turned on and to increase a driving voltage for turning on the high-side switch by a charged voltage; a buffer configured to output a control signal for controlling the high-side switch; a latch configured to receive the control signal at a first input terminal, retain the control signal, and output the control signal to the high-side switch; and a switch configured to receive the control signal from the latch and deactivate the buffer.

Abstract: A charge and discharge signal circuit includes: high side transistors connected in series; low side transistors connected in series; high side drive circuits; low side drive circuits; and a drive signal generation circuit, wherein each drive circuit includes: a level shifter; a capacitor switch string connected in series, being connected in parallel with the transistor; and a drive part, to which an output of the level shifter is supplied, at least one pair of neighboring ones of the level shifters are commonly formed, and two neighboring ones of the drive parts receive a same output from the common shifters.

Abstract: An oscillator includes a transformer, a first capacitor, a first transistor, a depletion or native second transistor, and a current control circuit. The transformer includes a primary winding configured to receive an input voltage and a secondary winding configured to boost the input voltage to generate an output voltage. The first capacitor is configured to form an LC resonant circuit together with the secondary winding to cause oscillation operation, the first transistor is connected in series with the primary winding, and the output voltage is applied to a control terminal of the first transistor. The depletion or native second transistor is connected in series with the primary winding and the first transistor, and the current control circuit is configured to adjust a control voltage applied to a control terminal of the second transistor to control a current flowing through the first winding.

Abstract: An oscillator includes a transformer, a first capacitor, a first transistor, a depletion or native second transistor, and a current control circuit. The transformer includes a primary winding configured to receive an input voltage and a secondary winding configured to boost the input voltage to generate an output voltage. The first capacitor is configured to form an LC resonant circuit together with the secondary winding to cause oscillation operation, the first transistor is connected in series with the primary winding, and the output voltage is applied to a control terminal of the first transistor. The depletion or native second transistor is connected in series with the primary winding and the first transistor, and the current control circuit is configured to adjust a control voltage applied to a control terminal of the second transistor to control a current flowing through the first winding.

Abstract: A charge and discharge signal circuit includes: high side transistors connected in series; low side transistors connected in series; high side drive circuits; low side drive circuits; and a drive signal generation circuit, wherein each drive circuit includes: a level shifter; a capacitor switch string connected in series, being connected in parallel with the transistor; and a drive part, to which an output of the level shifter is supplied, at least one pair of neighboring ones of the level shifters are commonly formed, and two neighboring ones of the drive parts receive a same output from the common shifters.

Abstract: A DC-DC converter includes: an inductor; a first capacitor and a second capacitor; a plurality of switching elements coupled to the inductor, the first capacitor, and the second capacitor; a control circuit configured to control the plurality of switching elements to be switched ON/OFF such that a connection form of the inductor, the first capacitor, and the second capacitor is alternately switched between a first form where the inductor, the first capacitor, and the second capacitor are coupled in series such that the first capacitor and the second capacitor are charged and a second form where the inductor, the first capacitor, and the second capacitor are coupled in parallel such that the first capacitor and the second capacitor are discharged; and a detection circuit configured to detect a difference between each of a voltage across the first capacitor and a voltage across the second capacitor.

Abstract: A charge and discharge signal circuit includes: high side transistors connected in series; low side transistors connected in series; high side drive circuits; low side drive circuits; and a drive signal generation circuit, wherein each drive circuit includes: a high side level shifter; a high side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the high side transistor; and a high side drive part, to which an output of the high side level shifter is supplied, and each of the low side drive circuits includes: a low side level shifter; a low side capacitor switch string of a capacitor and a switch element connected in series, being connected in parallel with the low side transistor; and a low side drive part, to which an output of the low side level shifter is supplied.

Abstract: A DC-DC converter includes: a high-side switch; a low-side switch coupled to the high-side switch in series; a capacitor configured to be charged while the low-side switch is turned on and to increase a driving voltage for turning on the high-side switch by a charged voltage; a buffer configured to output a control signal for controlling the high-side switch; a latch configured to receive the control signal at a first input terminal, retain the control signal, and output the control signal to the high-side switch; and a switch configured to receive the control signal from the latch and deactivate the buffer.

Abstract: A multiphase clock generation circuit includes: a first frequency divider to generate a first intermediate clock and a second intermediate clock; a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock; a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock; a selector to supply one of the second intermediate clock and a value to the third frequency divider in response to a switching signal; an error detection circuit to detect an error in a phase relationship between the output clock of the first group and the output clock of the second group; and a re-reset circuit to output the switching signal to the selector based on the error.

Abstract: An electrical circuit includes a first path including even-number inverters connected in series from a first node serving as an input side to a second node serving as an output side, a second path including even-number inverters connected in series from the second node serving as an input side to the first node serving as an output side, a latch circuit providing a connection between the first node and the second node such that a logical value of the first node and a logical value of the second node are opposite to each other, and one or more control signal paths to supply one or more control signals to the latch circuit to provide and sever a connection between the latch circuit and a power supply.

Abstract: A frequency synthesizer includes a voltage-controlled oscillator, a frequency range tuning circuit which detects a frequency control code that sets a voltage-controlled frequency range of the voltage-controlled oscillator corresponding to the frequency division ratio which is variably-set, and a frequency control code memory which stores the frequency control code detected by the frequency range tuning circuit corresponding to the frequency division ratio. In an initialization interval, the frequency range tuning circuit detects the frequency control code corresponding to the frequency division ratio which is variably-set, and the frequency control code memory stores the frequency control code which is detected. In a normal operation interval, in response to the frequency selection signal, the frequency control code, which is stored in the frequency control code memory and corresponds to the frequency division ratio which is variably-set, is output to the voltage-controlled oscillator.

Abstract: A multiphase clock generation circuit includes: a first frequency divider to generate a first intermediate clock and a second intermediate clock; a second frequency divider to generate output clocks of a first group including a first output clock and a second output clock; a third frequency divider to generate output clocks of a second group including a third output clock and a fourth output clock; a selector to supply one of the second intermediate clock and a value to the third frequency divider in response to a switching signal; an error detection circuit to detect an error in a phase relationship between the output clock of the first group and the output clock of the second group; and a re-reset circuit to output the switching signal to the selector based on the error.

Abstract: There is provided a semiconductor device having a voltage-controlled oscillator outputting an output clock signal; N pieces of control units generating a frequency-divided clock signal by frequency-dividing the output clock signal, comparing a reference clock signal and the frequency-divided clock signal, and outputting an output signal based on a comparison result; an adder adding output signals from each of the control units; and a low-pass filter filtering an output of the adder and outputting to the voltage-controlled oscillator, wherein setting information related to a frequency division ratio made of N pieces of data cycled and supplied in a sequence in synchronization with the frequency-divided clock signal is supplied to each of the control units with initial values made different from one another and a frequency-division operation and a comparison operation are performed thereby to form a moving average filter by N pieces of control units and to reduce a quantization noise, so that occurrence of a sp

Abstract: A clock signal generation apparatus includes a clock signal generation circuit generating a plurality of clock signals, and a self-test circuit measuring a phase difference of one pair of clock signals. The self-test circuit includes a clock signal selection circuit selecting the pair of clock signals among the plurality of clock signals, a phase detection circuit generating a phase difference pulse signal, a test signal generation circuit generating a test signal having a frequency which is lower than the phase difference pulse signal, and a counter circuit counting the pulse number of the test signal.

Abstract: An electrical circuit includes a first path including even-number inverters connected in series from a first node serving as an input side to a second node serving as an output side, a second path including even-number inverters connected in series from the second node serving as an input side to the first node serving as an output side, a latch circuit providing a connection between the first node and the second node such that a logical value of the first node and a logical value of the second node are opposite to each other, and one or more control signal paths to supply one or more control signals to the latch circuit to provide and sever a connection between the latch circuit and a power supply.

Abstract: There is provided a semiconductor device having a voltage-controlled oscillator outputting an output clock signal; N pieces of control units generating a frequency-divided clock signal by frequency-dividing the output clock signal, comparing a reference clock signal and the frequency-divided clock signal, and outputting an output signal based on a comparison result; an adder adding output signals from each of the control units; and a low-pass filter filtering an output of the adder and outputting to the voltage-controlled oscillator, wherein setting information related to a frequency division ratio made of N pieces of data cycled and supplied in a sequence in synchronization with the frequency-divided clock signal is supplied to each of the control units with initial values made different from one another and a frequency-division operation and a comparison operation are performed thereby to form a moving average filter by N pieces of control units and to reduce a quantization noise, so that occurrence of a sp

Abstract: A clock signal generation apparatus includes a clock signal generation circuit generating a plurality of clock signals, and a self-test circuit measuring a phase difference of one pair of clock signals. The self-test circuit includes a clock signal selection circuit selecting the pair of clock signals among the plurality of clock signals, a phase detection circuit generating a phase difference pulse signal, a test signal generation circuit generating a test signal having a frequency which is lower than the phase difference pulse signal, and a counter circuit counting the pulse number of the test signal.

Abstract: A frequency synthesizer includes a voltage-controlled oscillator, a frequency range tuning circuit which detects a frequency control code that sets a voltage-controlled frequency range of the voltage-controlled oscillator corresponding to the frequency division ratio which is variably-set, and a frequency control code memory which stores the frequency control code detected by the frequency range tuning circuit corresponding to the frequency division ratio. In an initialization interval, the frequency range tuning circuit detects the frequency control code corresponding to the frequency division ratio which is variably-set, and the frequency control code memory stores the frequency control code which is detected. In a normal operation interval, in response to the frequency selection signal, the frequency control code, which is stored in the frequency control code memory and corresponds to the frequency division ratio which is variably-set, is output to the voltage-controlled oscillator.

Abstract: A level down converter having a first inverter supplied a first power supply voltage, and outputting signals made by logical inversions of input signals, and a second inverter supplied a second power supply voltage being lower than the first power supply voltage, and outputting signals made by logical inversions of output signals from the first inverter, is provided. The first inverter contains a transistor including a gate insulation film having a first film thickness. The second inverter contains a transistor including a gate insulation film having a second film thickness which is thinner than the first film thickness.