Abstract: A semiconductor device and a highly reliable circuit are realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.

Abstract: A semiconductor device and a highly reliable circuit are realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.

Abstract: A highly reliable circuit is realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.

Abstract: A highly reliable circuit is realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.

Abstract: Disclosed is a frequency divider including first to fifth FFs(flip-flops), each of which receives a common clock signal and samples and outputs an input signal responsive to an effective edge of the clock, an output signal of the 1st FF being supplied to the 2nd FF, a first logic gate which receives an output signal of the 2nd FF and a first control signal and outputs the output signal of the 2nd FF, when the first control signal is of a first value, and outputs a predetermined value, when the first control signal is of a second value, the output signal of the first logic gate being supplied to an input of the 3rd FF; a second logic gate which receives an output signal of the 1st FF and a second control signal and outputs an output signal of the 1st FF, when the second control signal is of the first value and outputs the predetermined value, when the second control signal is of the second value, the output signal of the second logic gate being supplied to the 4th FF; and a third logic gate which receives an o

Abstract: Disclosed is a frequency divider including first to fifth FFs(flip-flops), each of which receives a common clock signal and samples and outputs an input signal responsive to an effective edge of the clock, an output signal of the 1st FF being supplied to the 2nd FF, a first logic gate which receives an output signal of the 2nd FF and a first control signal and outputs the output signal of the 2nd FF, when the first control signal is of a first value, and outputs a predetermined value, when the first control signal is of a second value, the output signal of the first logic gate being supplied to an input of the 3rd FF; a second logic gate which receives an output signal of the 1st FF and a second control signal and outputs an output signal of the 1st FF, when the second control signal is of the first value and outputs the predetermined value, when the second control signal is of the second value, the output signal of the second logic gate being supplied to the 4th FF; and a third logic gate which receives an o

Abstract: A semiconductor device includes an output path; an input path; and a test signal generating circuit. The test signal generating circuit generates an input test data signal by changing at least one of an amplitude and a phase of an output test data signal which is generated from a test data in the semiconductor device and transferred on the output path, and supplies the input test data signal onto the input path. The output path and the input path are tested by using the output test data signal and the input test data signal, respectively.

Abstract: A noise canceller circuit capable of suppressing power supply noise, produced by transition of a data signal, even in case a data signal is increased in speed. The noise canceller circuit includes an output buffer 20 for outputting a first binary signal that may undergo transition at a timing synchronized with clock signals, and a second output buffer 21 for outputting a second binary signal which has undergone transition in case the first binary signal does not undergo transition at the above timing and for outputting the second binary signal without transition in case the first binary signal has undergone transition at the above timing. The respective output circuits of the output buffers 20, 21 are the same and are constructed so that the respective power supply sources VDD and the ground GND are common to the buffer circuits. A capacitor 24 for absorbing the noise is provided across the power supply and the ground.

Abstract: A semiconductor device includes an output path; an input path; and a test signal generating circuit. The test signal generating circuit generates an input test data signal by changing at least one of an amplitude and a phase of an output test data signal which is generated from a test data in the semiconductor device and transferred on the output path, and supplies the input test data signal onto the input path. The output path and the input path are tested by using the output test data signal and the input test data signal, respectively.

Abstract: A noise canceller circuit capable of suppressing power supply noise, produced by transition of a data signal, even in case a data signal is increased in speed. The noise canceller circuit includes an output buffer 20 for outputting a first binary signal that may undergo transition at a timing synchronized with clock signals, and a second output buffer 21 for outputting a second binary signal which has undergone transition in case the first binary signal does not undergo transition at the above timing and for outputting the second binary signal without transition in case the first binary signal has undergone transition at the above timing. The respective output circuits of the output buffers 20, 21 are the same and are constructed so that the respective power supply sources VDD and the ground GND are common to the buffer circuits. A capacitor 24 for absorbing the noise is provided across the power supply and the ground.

Abstract: A variable current source using weighted current sources for preventing degradation of an accuracy of an output current due to deviations in manufacturing. The variable current source is formed by a series of binary weighted current sources having a first current source of the lowest order on a lower side with a current value equal to or lower than a tolerance current value which is a resolution for an output current. Assuming that e is a deviation rate of the variations due to manufacturing, a current value Ia.sub.k of a k.sup.th current source in current value increasing order is derived by adding a deviation to a designed current value of the current source. The current value is set to be equal to or lower than a sum of a higher deviation current value, derived by adding a deviation to a designed current value of a current source below the k.sup.th current source immediately and a lower deviation current value, derived by subtracting the deviation from the designed value of the k-1.sup.

Abstract: There is provided a semiconductor integrated circuit device including an external source voltage detector for keeping transmitting a first signal after detecting that an absolute value of external source voltage provided externally of the semiconductor integrated circuit device has exceeded a first threshold voltage, and an internal source voltage generator for generating a constant internal source voltage regardless of the external source voltage while the absolute value of the external source voltage is in a predetermined range, and providing the external source voltage as it is as an internal source voltage while the first signal is being kept transmitted. The semiconductor integrated circuit device makes it possible to externally control an internal source voltage to be applied to an internal circuit mounted in an IC chip without addition of control terminals over a wide range of an external source voltage.

Abstract: A bipolar transistor constant voltage source circuit includes a first transistor having a collector connected through a first resistor to VCC, an emitter connected through a second resistor to ground, and a base connected to receive a reference voltage. The collector of the first transistor is connected to a base of a second transistor having a collector connected to VCC and an emitter connected to the ground through third and fourth resistors connected in series. A connection node between the third and fourth resistors is connected to a base of a third transistor having a collector connected through a fifth resistor to VCC and an emitter connected through a sixth resistor to the ground.