Abstract: A controller capable of improving the disappearance resistance of a synthetic resin coating of a diaphragm, and a vaporization supply device comprising the controller. The controller includes a body having an inflow passage and an outflow passage, a valve seat provided between the inflow passage and the outflow passage, a diaphragm capable of being seated on or separated from the valve seat, and an actuator for causing the diaphragm to be seated on and separated from the valve seat. The material of the valve seat is nickel-based, and the diaphragm is provided with a synthetic resin coating on a surface of a side to be brought into contact with the valve seat.

Abstract: A lower resist (2) is applied on a semiconductor substrate (1). An upper resist (3) is applied on the lower resist (2). A first opening (4) is formed in the upper resist (3) by exposure and development and the lower resist (2) is dissolved with a developer upon the development to form a second opening (5) having a width wider than that of the first opening (4) below the first opening (4) so that a resist pattern (6) in a shape of an eave having an undercut is formed. Baking is performed to thermally shrink the upper resist (3) to bent an eave portion (7) of the upper resist (3) upward. After the baking, a metal film (8) is formed on the resist pattern (6) and on the semiconductor substrate (1) exposed at the second opening (5). The resist pattern (6) and the metal film (8) is removed on the resist pattern (6) and the metal film (8) is left on the semiconductor substrate (1) as an electrode (9).

Abstract: The disclosure provides a temperature compensation circuit that generates a temperature-compensated current and an integrated semiconductor circuit using the temperature compensation circuit. The temperature compensation circuit includes: a first PTAT current source which has a first emitter area ratio and generates a first current, the first current having a first temperature coefficient proportional to the absolute temperature; a second PTAT current source which has a second emitter area ratio and generates a second current, the second current having a second temperature coefficient proportional to the absolute temperature; an adjustment circuit which adjusts the current generated by the first PTAT current source; and a differential circuit which outputs the difference between the current adjusted by the adjustment circuit and the current generated by the second PTAT current source.

Abstract: The disclosure provides a temperature compensation circuit that generates a temperature-compensated current and an integrated semiconductor circuit using the temperature compensation circuit. The temperature compensation circuit includes: a first PTAT current source which has a first emitter area ratio and generates a first current, the first current having a first temperature coefficient proportional to the absolute temperature; a second PTAT current source which has a second emitter area ratio and generates a second current, the second current having a second temperature coefficient proportional to the absolute temperature; an adjustment circuit which adjusts the current generated by the first PTAT current source; and a differential circuit which outputs the difference between the current adjusted by the adjustment circuit and the current generated by the second PTAT current source.

Abstract: Provided is a constant current circuit supplying a temperature-compensated constant current. The constant current circuit includes a BGR circuit, a temperature dependent current generator, a reference current generator, and an output current generator. The BGR circuit generates a reference voltage with low voltage dependence. The temperature dependent current generator generates a temperature dependent current having a positive temperature coefficient. The reference current generator generates a temperature-compensated reference current by using the reference voltage and the temperature dependent current. The output current generator generates an output current based on the reference current generated by the reference current generator.

Abstract: The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: The present invention provides an oscillator circuit and a semiconductor integrated circuit, which can suppress the upper limit of the frequency of a clock signal due to an error of the constant current circuit. The oscillator circuit of the present invention includes a constant current circuit, an oscillator, and a current limiting circuit. The constant current circuit generates a first output current according to a supply voltage. The current limiting circuit receives the first output current and generates a second output current, and establishes an upper limit for the second output current when the supply voltage drops below a lower limit of a guaranteed operational range of the constant current circuit. The oscillator generates a clock signal according to the second output current. By establishing the upper limit for the second output current, the upper limit of the frequency of the clock signal can be suppressed.

Abstract: What is provided is a voltage-generating circuit that uses dynamic reference voltage to accurately control the step-up of a generated voltage. A voltage-generating circuit 100 of the invention includes a charge pump 110 outputting voltage Vpump, a regulator 120, and a controlling circuit 140. The regulator 120 includes a comparator 122 and a comparator 132. The comparator 122 compares voltage Vdivide generated by the charge pump 110 with a reference voltage Vref, and outputs a comparison result CMP_OUT. The comparator 132 compares voltage Vdivide2 generated by the charge pump 110 with a reference voltage VrefRRC with a controlled rising speed, and outputs a comparison result CMP2_OUT. The controlling circuit 140 controls the charge pump 110 based on CMP_OUT and CMP2_OUT.

Abstract: Provided is a constant current circuit supplying a temperature-compensated constant current. The constant current circuit includes a BGR circuit, a temperature dependent current generator, a reference current generator, and an output current generator. The BGR circuit generates a reference voltage with low voltage dependence. The temperature dependent current generator generates a temperature dependent current having a positive temperature coefficient. The reference current generator generates a temperature-compensated reference current by using the reference voltage and the temperature dependent current. The output current generator generates an output current based on the reference current generated by the reference current generator.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: What is provided is a voltage-generating circuit that uses dynamic reference voltage to accurately control the step-up of a generated voltage. A voltage-generating circuit 100 of the invention includes a charge pump 110 outputting voltage Vpump, a regulator 120, and a controlling circuit 140. The regulator 120 includes a comparator 122 and a comparator 132. The comparator 122 compares voltage Vdivide generated by the charge pump 110 with a reference voltage Vref, and outputs a comparison result CMP_OUT. The comparator 132 compares voltage Vdivide2 generated by the charge pump 110 with a reference voltage VrefRRC with a controlled rising speed, and outputs a comparison result CMP2_OUT. The controlling circuit 140 controls the charge pump 110 based on CMP_OUT and CMP2_OUT.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Abstract: The present invention provides an organometallic compound represented by the general formula (1) or (2), process for producing the same, metathesis reaction catalyst containing the same, polymerization process using the same catalyst and polymer produced by the same polymerization process:

Abstract: The present invention provides an organometallic compound represented by the general formula (1) or (2), process for producing the same, metathesis reaction catalyst containing the same, polymerization process using the same catalyst and polymer produced by the same polymerization process: 1

Abstract: A constant-current polarization voltage detecting method includes step of feeding to a detecting electrode a predetermined minute current in a pulse form, and detecting sequentially a polarization voltage at each time of feeding the pulsating current, in an electrochemical analysis in solution. The polarization voltage is detected after a lapse of a predetermined time from the initiation of feeding the pulsating current at each time. A Karl Fischer's moisture content analyzing apparatus can utilize such a method.