Abstract: An insulated gate semiconductor device comprises a channel region of compound semiconductor of one conductivity type, source and drain regions of the other conductivity type spaced apart by the channel region, a gate insulation film provided on the channel region, a gate electrode provided on the insulating film and a silicon monocrystal thin film having a thickness of 100 atoms or less inserted between the channel region and the gate insulation film.

Abstract: A semiconductor device of the complementary metal-insulator semiconductor type is composed of a pair of N-type metal oxide semiconductor transistor formed on a P-type silicon substrate and P-type metal oxide semiconductor transistor formed on an n-type well disposed within the p-type substrate. An isolation tranch is disposed between the pair of adjacent transistors, and has one sidewall bordering the well, another opposed sidewall bordering the substrate, and a bottom wall. A selective epitaxial film of p-type is selectively epitaxially deposited on the sidewalls and bottom wall of the trench. The epitaxial film has a dopant density greater than that of the substrate. An insulation oxide material is filled within the trench so as to effectively isolate the pair of transistors from each other.

Abstract: In molecular beam epitaxial growth of GaAs substrate, a compound semiconductor thin film having Ga and As is grown by Ga beam and As beam in MBE chamber and then the substrate is transferred to an annealing chamber where the substrate is annealed under As vapor pressure. The above process is repeated to a predetermined layer level whereby it eliminates divergence from stoichiometric.

Abstract: The present invention provides a fabrication method of miniature insulated gate semiconductor devices such as MOS and CMOS in which their gates are formed by self-alignment, and in addition, provision of lightly doped drain (LDD) structure is easy. Therefore the present invention is extremely effective in the fabrication of miniature semiconductor devices which can be highly integrated and can operate at high speed.

Abstract: According to the present invention, a thin film transistor of a vertical type in which an electric current flows in a vertical direction not parallel to a base plate surface. A high resistance semiconductor thin film, a gate insulated film and gate electrode are sequentially shaped on a side surface of drain and source main electrodes stacked as multi-layers via an insulated film, whereby a channel length L is determined by a thickness of said insulated film.

Abstract: A method of manufacturing semiconductor device wherein the self-alignment technique is employed to simplify the manufacturing process and includes the steps of successively depositing multiple layer masking films comprising a first, a second and a third masking films on an n-type Si region, forming an island region of the multiple layer films and a peripheral portion of the second masking film which is etched away, by side-etching, from the edges of the other masking films, selectively forming an oxidized film, selectively etching the first oxidized film using the second masking film as a mask and forming fine contact windows between the selectively formed oxidized film and the first masking film, depositing a semiconductor thin film, lifting-off the semiconductor thin film by removing the second and third masking films and leaving a portion of the semiconductor film which contacts the windows, oxidizing the surface of the semiconductor thin film and removing the first masking film.

Abstract: A novel MOS field effect transistor which operates at high speed and with low power consumption has impurity doped source and drain regions deposited at 850.degree. C. or less by molecular layer epitaxial growth method. The molecular layer epitaxial growth is concurrently carried out with the control of impurity doping concentration so that the layers epitaxially deposited has a lightly doped region and a heavily doped region. Since the thickness of the growth layer can be controlled with a degree of accuracy on the order of an atom layer and thermal diffusions can remarkably be reduced by the low deposition temperature, an overlap of a gate over each of the source and drain regions can be reduced to 500 .ANG. or less.

Abstract: Insulated-gate-field-effect transistors are disposed on an insulating substrate as a matrix. Each gate electrode of the transistors is covered with each gate insulating film and semiconductor film acting as a channel of the transistors, respectively.

Abstract: The present invention aims to form a MOST, for example a MOS-SIT, whose impurity density in a channel region is lower than an ordinary MOST on a substrate or is formed in an epitaxial growth layer on a well.

Abstract: A gate insulating film, a high-resistivity semiconductor film, a low-resistivity semiconductor film and if necessary a conducting film are successively deposited in lamination without exposing them to any oxidizing atmosphere including atmospheric air, and then the source and drain electrodes are selectively formed.

Abstract: A method of manufacturing a thin film transistor array is simplified by processes to form source and drain electrodes at least of ITO film for pixel electrodes on a gate insulating film covering gate electrode and to form islands of an amorphous semiconductor film and a light shield film in the same masking process on the source and the drain electrodes.

Abstract: A method of manufacturing an integrated circuit device including vertical static induction transistors (SIT) having a first recess between the gate region and the drain (or source) region to reduce the capacitance between both regions and a second recess on an outer surface of the SIT gate to reduce the gate capacitance and a minority carrier storage. The method includes the steps of removing a masking film on the SIT channel region while leaving the masking film at the portions of the gate region and the drain region; forming the first and the second recesses in the channel region; locally oxidizing the exposed channel region; and forming the gate region and the drain region by removing the masking film.

Abstract: An integrated logic circuit uses thin film IGFET loads integrated with complementary vertical JFET drivers, the IGFETs and JFETs being connected together gate to gate as the input and drain to drain as the effective output node.

Abstract: A method of fabricating integrated circuits comprises forming a concave portion having bottom and side faces on a semiconductor single-crystal substrate, forming an insulating film on the faces of the concave portion except for at least a portion of the bottom face, and forming a first semiconductor growth layer on the insulating film-free portion of the bottom face of the concave portion by chemical vapor deposition using a mixture gas containing semiconductor chloride and hydrogen such that the top surface of the growth layer is the same level as the upper face of the substrate in the region adjoining the concave portion. Semiconductor devices are then fabricated in the substrate and growth layer.

Abstract: A method of fabricating a semiconductor device comprising forming an island-shaped multi-layered structure of oxides and nitrides on the surface of a semiconductor. The multi-layered structure is selectively etched to define diffusion windows for forming a semiconductor structure in the semiconductor surface having a central region of one conductivity type surrounded by another region of a different conductivity type. A second island-like multi-layered structure is formed and is etched for controlling the duration of the etching steps by controlling the amount that the masks lift off from the insulation layers subjected to etching. The etching is carried out by side etching.

Abstract: A method of fabricating a vertical static induction semiconductor device comprising depositing a polycrystalline silicon film on a single crystal silicon layer, and forming an insulating film comprised of silicon nitride on the polycrystalline film. The insulating film is selectively etched to form islands of the insulating film overlying areas where a gate region and a main electrode region of the semiconductor device are to be formed. An oxide film is formed on the surface regions exposed by etching, and the oxide film is used as a mask for controlling introduction of impurity atoms to form the gate region and the main electrode region.

Abstract: A method of fabricating a semiconductor integrated circuit device wherein a substrate having a particular crystallographic orientation is selectively etched so as to form surface depressions of different depths. An epitaxial layer is grown from a Si--H--Cl system on the surface of the substrate having the surface depressions formed therein. The epitaxial layer is grown under conditions effective to achieve faster lateral growth than vertical growth so as to form the epitaxial layer with regions of three different thicknesses. Subsequently, additional regions of the semiconductor integrated circuit are formed in the epitaxial layer regions of different thicknesses so as to complete the device.