Patents by Inventor Masaharu Kinoshita
Masaharu Kinoshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140065789Abstract: In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.Type: ApplicationFiled: November 10, 2013Publication date: March 6, 2014Applicant: Hitachi, Ltd.Inventors: Yoshitaka SASAGO, Masaharu KINOSHITA, Mitsuharu TAI, Takashi KOBAYASHI
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Patent number: 8642988Abstract: A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.Type: GrantFiled: August 17, 2012Date of Patent: February 4, 2014Assignee: Hitachi, Ltd.Inventors: Masaharu Kinoshita, Yoshitaka Sasago, Takashi Kobayashi, Hiroyuki Minemura
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Patent number: 8604456Abstract: Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.Type: GrantFiled: February 6, 2012Date of Patent: December 10, 2013Assignee: Hitachi, Ltd.Inventors: Masaharu Kinoshita, Yoshitaka Sasago, Norikatsu Takaura
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Patent number: 8592789Abstract: In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.Type: GrantFiled: May 17, 2011Date of Patent: November 26, 2013Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Mitsuharu Tai, Takashi Kobayashi
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Patent number: 8563961Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced.Type: GrantFiled: December 13, 2010Date of Patent: October 22, 2013Assignee: Hitachi, Ltd.Inventors: Yoshitaka Sasago, Akio Shima, Satoru Hanzawa, Takashi Kobayashi, Masaharu Kinoshita, Norikastsu Takaura
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Patent number: 8541768Abstract: A technique used for a semiconductor device formed by stacking multiple structural bodies each having a semiconductor device, for preventing generation of thermal load on a structural body at a lower layer which is caused by a laser used in a step of forming a structural body at an upper layer. In a phase-change memory including multiple stacked memory matrices, a metal film is disposed between a memory matrix at a lower layer and a memory matrix at an upper layer formed over the memory matrix at the lower layer, in which the laser used for forming the memory matrix is reflected at the metal film and prevented from transmitting the metal film, thereby preventing the phase-change material layer, etc. in the memory matrix at the lower layer from being directly heated excessively by the laser.Type: GrantFiled: May 28, 2011Date of Patent: September 24, 2013Assignee: Hitachi, Ltd.Inventors: Akio Shima, Yoshitska Sasago, Toshiyuki Mine, Masaharu Kinoshita
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Publication number: 20130234101Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.Type: ApplicationFiled: November 22, 2010Publication date: September 12, 2013Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Takahiro Morikawa, Akio Shima, Takashi Kobayashi
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Publication number: 20130228739Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.Type: ApplicationFiled: December 6, 2010Publication date: September 5, 2013Inventors: Yoshitaka Sasago, Masaharu Kinoshita, Mitsuharu Tai, Akio Shima, Kenzo Kurotsuchi, Takashi Kobayashi
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Publication number: 20130141968Abstract: The purpose of the present invention is to improve a rewriting transmission rate and reliability of a phase change memory. To attain the purpose, a plurality of phase change memory cells (SMC or USMC) which are provided in series between a word line (2) and a bit line (3) and have a selection element and a storage element that are parallel connected with each other are entirely set, and after that, a part of the cells corresponding to a data pattern is reset. Alternatively, the reverse of the operation is carried out.Type: ApplicationFiled: August 26, 2011Publication date: June 6, 2013Inventors: Yoshitaka Sasago, Hiroyuki Minemura, Takashi Kobayashi, Toshimichi Shintani, Satoru Hanzawa, Masaharu Kinoshita
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Patent number: 8427865Abstract: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.Type: GrantFiled: April 5, 2012Date of Patent: April 23, 2013Assignee: Hitachi, Ltd.Inventors: Akio Shima, Yoshitaka Sasago, Masaharu Kinoshita, Toshiyuki Mine, Norikatsu Takaura, Takahiro Morikawa, Kenzo Kurotsuchi, Satoru Hanzawa
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Publication number: 20130075684Abstract: A non-volatile memory device includes: a first line extending along a main surface of a substrate; a stack provided above the first line; a second line formed above the stack; a select element provided where the first and second lines intersect, the select element adapted to pass current in a direction perpendicular to the main surface; a second insulator film provided along a side surface of the stack; a channel layer provided along the second insulator film; an adhesion layer provided along the channel layer; and a variable resistance material layer provided along the adhesion layer, wherein the first and second lines are electrically connected via the select element and channel layer, a contact resistance via the adhesion layer between the channel layer and variable resistance material layer is low, and a resistance of the adhesion layer is high with respect to an extending direction of the channel layer.Type: ApplicationFiled: August 17, 2012Publication date: March 28, 2013Inventors: Masaharu Kinoshita, Yoshitaka Sasago, Takashi Kobayashi, Hiroyuki Minemura
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Patent number: 8337282Abstract: The present invention provides a polishing pad which can improve qualities of an object to be polished by improving the flatness of the object. A polishing surface 1a of a polishing pad 1 is subjected to a mechanical process, such as buffing, so that the flatness of the surface is improved, and corrugations on the polishing surface have a cycle of 5 mm-200 mm and a largest amplitude of 40 ?m or less. As a result, the flatness of the object polished by the polishing pad 1, such as a silicon wafer, is improved.Type: GrantFiled: August 31, 2007Date of Patent: December 25, 2012Assignee: Nitta Haas IncorporatedInventors: Jaehong Park, Shinichi Matsumura, Kouichi Yoshida, Yoshitane Shigeta, Masaharu Kinoshita
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Publication number: 20120262901Abstract: Disclosed is a display device capable of achieving a decorative effect by utilizing a color filter at the front of a light-emitting display unit. Also disclosed is a meter device using the display device. Specifically disclosed is a display device comprising a light-emitting display unit and a color filter, which is arranged at the front of the light-emitting display unit. A light-emitting element for decoration is provided on the outside of the light-emitting display unit. The color filter is provided with a light-discharging surface for discharging the light from the light-emitting element for a decorative appearance in the forward direction.Type: ApplicationFiled: November 30, 2009Publication date: October 18, 2012Applicants: Toyota Shatai Kabushiki Kaisha, Toyota Jidosha Kabushiki Kaisha, Yazaki CorporationInventors: Hiroaki Ichihara, Masaharu Kinoshita, Yoshifumi Tatsuta, Takahiro Shimada, Koji Nomura, Masato Minakata, Koji Aikawa
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Publication number: 20120248399Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced.Type: ApplicationFiled: December 13, 2010Publication date: October 4, 2012Inventors: Yoshitaka Sasago, Akio Shima, Satoru Hanzawa, Takashi Kobayashi, Masaharu Kinoshita, Norikastsu Takaura
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Publication number: 20120211717Abstract: A semiconductor memory device in which the cell area can be decreased and the minimum feature size is not restricted by the thickness of the material forming the memory cell. In a semiconductor memory device, a gate insulating film, a channel extending in a direction X, and a resistance change element extending in the direction X are formed successively above multiple word lines extending in a direction Y, and a portion of the channel and a portion of the resistance change element are disposed above each of the plurality of the word lines. Such configuration can decrease the cell area and ensure the degree of design freedom.Type: ApplicationFiled: January 13, 2012Publication date: August 23, 2012Inventors: Masaharu KINOSHITA, Yoshitaka SASAGO, Takashi KOBAYASHI
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Publication number: 20120211718Abstract: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.Type: ApplicationFiled: April 5, 2012Publication date: August 23, 2012Inventors: AKIO SHIMA, Yoshitaka Sasago, Masaharu Kinoshita, Toshiyuki Mine, Norikatsu Takaura, Takahiro Morikawa, Kenzo Kurotsuchi, Satoru Hanzawa
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Publication number: 20120132879Abstract: Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.Type: ApplicationFiled: February 6, 2012Publication date: May 31, 2012Inventors: MASAHARU KINOSHITA, Yoshitaka Sasago, Norikatsu Takaura
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Patent number: 8169819Abstract: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.Type: GrantFiled: January 17, 2010Date of Patent: May 1, 2012Assignee: Hitachi, Ltd.Inventors: Akio Shima, Yoshitaka Sasago, Masaharu Kinoshita, Toshiyuki Mine, Norikatsu Takaura, Takahiro Morikawa, Kenzo Kurotsuchi, Satoru Hanzawa
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Publication number: 20120074368Abstract: A semiconductor memory device having a diode and a transistor connected in series, which prevents carriers from going from the diode into the transistor, thereby reducing the possibility of transistor deterioration. A structure to annihilate carriers from the diode is provided between a channel layer of the transistor and a diode semiconductor layer of the diode where the carriers are generated.Type: ApplicationFiled: July 13, 2011Publication date: March 29, 2012Inventors: Yoshitaka SASAGO, Masaharu KINOSHITA, Mitsuharu TAI, Akio SHIMA, Takashi KOBAYASHI
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Patent number: 8132063Abstract: To realize a fast and highly reliable phase-change memory system of low power consumption, a semiconductor device includes: a memory device which includes a first memory array having a first area including a plurality of first memory cells and a second area including a plurality of second memory cells; a controller coupled to the memory device to issue a command to the memory device; and a condition table for storing a plurality of trial writing conditions. The controller performs trial writing in the plurality of second memory cells a plurality of times based on the plurality of trial writing conditions stored in the condition table, and determines writing conditions in the plurality of first memory cells based on a result of the trial writing. The memory device performs writing in the plurality of first memory cells based on the writing conditions instructed from the controller.Type: GrantFiled: July 26, 2011Date of Patent: March 6, 2012Assignee: Hitachi, Ltd.Inventors: Motoyasu Terao, Satoru Hanzawa, Hitoshi Kume, Minoru Ogushi, Yoshitaka Sasago, Masaharu Kinoshita, Norikatsu Takaura