Abstract: There is provided a video signal processing apparatus that makes it possible to realize a favorable display of pictures by increasing the detection accuracy of the video source of an input video signal and by using an appropriate scanning method for an output video signal in accordance with the determined type of video source.

Abstract: There is provided a video signal processing apparatus that makes it possible to realize a favorable display of pictures by increasing the detection accuracy of the video source of an input video signal and by using an appropriate scanning method for an output video signal in accordance with the determined type of video source.

Abstract: An apparatus and method in which a difference between lines in an input composite video signal is calculated. The difference is compared with a specified threshold to detect chrominance correlation. A difference between lines in a composite video signal which is delayed for a one-frame period is calculated. The difference is compared with the specified threshold to detect chrominance correlation. The difference between these chrominance correlations is calculated and is used as a motion detection signal. When this frame difference is smaller than a specified threshold, the motion detection signal is forcibly set to 0.

Abstract: A plurality of circuit blocks that output digital signals with different sampling frequencies are connected to data buses in common. One of outputs of the circuit blocks is selected and the output is sent to a sampling rate converter circuit block through the data buses. Each of the circuit blocks has a tri-state buffer at its output stage. With an output enable signal, a desired circuit block can be selected.

Abstract: A luminance and chrominance signal separation circuit in which, when its comparing circuits decide that the level of high-frequency components of a luminance signal is lower than a predetermined level, a switching circuit, controlled by a control circuit, selects and outputs a chrominance signal output from a BPF processing circuit.

Abstract: A video signal processing circuit used for a non-interlace television comprises an interfield interpolation circuit for carrying out interfield interpolation by using a video signal before one field of an input video signal to output interpolated line video signals corresponding to respective interline positions in one field. An intrafield interpolation circuit carries out intrafield interpolation by using video signals of a plurality of lines of the input video signal to output interpolated line video signals corresponding to respective interline positions in one field. A motion detector detects motion of the input video signal, and a weighting adder implements weighting to an output signal from the interfield interpolation circuit and an output signal from the intrafield interpolation circuit in accordance with a signal from the motion detector to add the weighted output signals.

Abstract: A television receiver for extended definition television carries out scanning line interpolation in a way that eliminates picture shift on the screen and ensures normal display when supplied with a non-standard video signal having a scanning line count of other than 262.5 lines per field. The television receiver includes a scanning line interpolation circuit, a normal video signal detection circuit and a interpolation controller. The scanning line interpolation circuit effects scanning line interpolation using either data in the current field or out-of-field data as per the result of motion detection in the picture. The normal video signal detection circuit distinguishes the normal video signal from other signals by detecting the number of scanning lines involved. The interpolation controller causes the scanning line interpolation circuit to effect scanning line interpolation using only the inside-field data if the supplied signal is a non-standard signal.

Abstract: An adaptive comb filter for separating at least one component of a video signal includes a filter input terminal for receiving the video signal, a first delay device for delaying the video signal by a first interval to produce a first delayed video signal, a second delay device for delaying the video signal by a second interval to produce a second delayed video signal, a first signal subtractor for producing a first difference signal proportional to a difference between the video signal and the first delayed video signal, a second subtractor for producing a second difference signal proportional to a difference between the first delayed video signal and the second delayed video signal, a first signal summing device for producing a first summation signal proportional to a summation of the first difference signal and the second difference signal, a signal selecting device for controllably selecting one of the first difference signal, the second difference signal and the first summation signal as the separated co

Abstract: Interpolated scan lines are produced in response to received video signals which are comprised of conventional interlaced scan lines constituting successive fields. A delay circuit, preferably formed of field memory devices, such as three cascaded field memories, functions to delay the received video signals to provide a first scanned line signal in a given field, the next succeeding scan line signal in that field, an interlaced scan line signal in the next succeeding field and an interlaced scan line signal in the next preceding field. A first combining circuit combines the signal values of the next succeeding field interlaced scan line signal and the next preceding field interlaced scan line signal to form a first combined scan line signal. A second combining circuit combines the signal values of the first scan line signal in the given field and the next succeeding scan line signal in that field to form a second combined scan line signal.

Abstract: Intermediate vertical synchronizing signals are generated to occur between the vertical synchronizing signals normally included in a conventional video signal. A first counter counts clock signals which are synchronized with the horizontal synchronizing signals normally included in the conventional video signal to provide a count representing the number of clock signals which are present in one-half of a field interval of that conventional video signal. The count provided by the first counter during the second preceding field interval is temporarily stored and compared to a count produced by a second counter which counts the clock signals from the beginning of the field interval. An intermediate vertical synchronizing signal is generated when the count of the second counter is equal to the stored count.

Abstract: A time-division bit number circuit that comprises a bit number expansion system and/or a bit number reduction system. The bit number expansion system converts an N bits signal to a 2N bits signal, while the bit number reduction system converts the 2N bits signal to the N bits signal where N is an integer. Thus, according to the time-division bit amount circuit, the number of memory can be saved, the area of circuit can be reduced and the pattern area of substrate can be reduced.

Abstract: A moving detection circuit which has a difference level generator which includes at least a frame delay circuit, and a vertical correlation detector which is connected to the difference signal generator and including a plurality of filters connected to the difference signal generator. A switching circuit for selecting one of the plurality of filters is provided and a control circuit is connected to the vertical correlation detector so as to control the switching circuit in response to the output level of the vertical correlation detector.

Abstract: A signal processing circuit for a moving detection circuit which has a coefficient generator which is connected to an output of a moving detection circuit. A level comparator is connected between the moving detection circuit and the coefficient generator and is also connected to a threshold voltage switch. An isolated-point eliminating circuit is connected between the level comparator and a time base filter which is connected at its output terminal to the input terminal of the coefficient generator. The coefficient generator includes a plurality of one bit delay devices which are connected in series and the plurality of one bit delay devices have a plurality of output terminals, and an adder is connected to the plurality of output terminals so as to add the output signals.

Abstract: In a memory control apparatus for providing various video display functions by means of a video memory into which video data constituting successive units, such as, frames or fields, or video information are written at repeatedly changing write addresses while concurrently reading out the data from repeatedly changing read-out addresses; the video memory is provided with at least four memory areas each having a capacity to store one of the units of video information, impending overtaking of the write and read-out addresses relative to each other is detected, and, in response to such detection, the one of the memory areas in which the data is being written or read-out is changed so as to maintain a separation of the write and read-out addresses sufficient to ensure avoidance of overtaking and consequent disturbance of the displayed image.

Abstract: In a picture-in-picture television receiver, the subpicture signal is A-D converted; the converted digital subpicture signal is latched in response a subpicture clock in synchronism with a subpicture synchronizing signal; the latched signal is latched again and stored in an image memory in response to a main picture synchronizing signal; and the latched signal is read from the image memory in synchronism with the main picture synchronizing signal, in order that the subpicture can stably be inserted in a predetermined area of the main picture by eliminating the unstable data duration during which variation in the subpicture signal is different for each bit signal thereof.

Abstract: A digital scan converter having an oscillator providing a clock signal used to scan-convert an input video signal to thereby produce a scan-converted output video signal, an automatic frequency control for controlling the oscillator in synchronism with a synchronizing signal separated from the input video signal and a counter for frequency-dividing the clock signal from the oscillator to thereby form a control signal used for controlling blanking of the input video signal. The counter also provides an address signal for a memory in which the video signal is temporarily stored during the scan converting operation. Since a composite blanking pulse for the input video signal is formed in synchronism with the address signal for the memory, it is possible to prevent appearance of a jitter of the composite blanking pulse on a display screen.

Abstract: A dark signal component below a predetermined level of a video signal is varied such that a dark peak level is made to coincide with a pedestal level by feedback control. According to this configuration, a signal component toward a white level side above the predetermined level is not changed by dark restoration, thus obtaining stable color reproduction and stable brightness which are not affected by the dark restoring operation.

Abstract: A CRT drive control circuit for automatically limiting beam current when it is too large. A brightness reduction control and a contrast reduction control are alternately applied in accordance with a dark level detection of a video signal.

Abstract: A synchronous detector for detecting an information signal modulated onto a carrier, such as a video IF signal, is disclosed in which there are provided a circuit for supplying the modulated information signal in the form of a vestigial sideband signal, a filter circuit coupled to the supplying circuit which includes a tuning circuit tuned to the frequency of the carrier on which the information signal is modulated, an emitter follower circuit connected to the output of the filter circuit, a limiter circuit connected to the filter circuit, for producing a switching carrier, and a multiplier having first and second input terminals coupled to the output of the limiter circuit and to the supplying circuit, for multiplying the modulated information signal and the switching carrier to obtain said information signal.

Abstract: A synchronous detector suitable for use in a color television receiver detects both a video signal and an audio IF signal, but in a fashion in which these two signals do not interfere with one another. In the detector, a tuner provides an IF signal in which the video signal and audio or sound IF signals are modulated on a carrier; a signal generator, such as a phase-locked loop, provides both a detecting signal synchronized with the carrier of the IF signal, and a comparing signal having the same frequency as the carrier of the IF signal but phase-shifted .pi./2 therefrom; a synchronous detecting circuit for synchronously detecting the IF signal by the detecting signal to produce the video signal; and a phase comparator for phase comparing the IF signal with the comparing signal to provide the sound IF signal. In one arrangement, the phase comparator provides a filtered version of the sound IF signal as an AFT control signal to control the fine tuning of the tuner.