Abstract: A semiconductor chip is divided into a first semiconductor region surrounded by pads and a region outside the pads. A memory is arranged at the region outside the pads. A memory arranged in the first semiconductor region and the memory arranged outside the pads are coupled to a bus interface unit via separate memory buses and a selector. The selector is driven by two phase, non-overlapping clock signals. A semiconductor integrated circuit device is provided that can easily accommodate for modification in the memory capacity of the memory and that can transfer signal/data at high speed with a low power consumption, irrespective of modification in bus interconnection length.

Abstract: A semiconductor chip is divided into a first semiconductor region surrounded by pads and a region outside the pads. A memory is arranged at the region outside the pads. A memory arranged in the first semiconductor region and the memory arranged outside the pads are coupled to a bus interface unit via separate memory buses and a selector. The selector is driven by two phase, non-overlapping clock signals. A semiconductor integrated circuit device is provided that can easily accommodate for modification in the memory capacity of the memory and that can transfer signal/data at high speed with a low power consumption, irrespective of modification in bus interconnection length.

Abstract: A semiconductor chip is divided into a first semiconductor region surrounded by pads and a region outside the pads. A memory is arranged at the region outside the pads. A memory arranged in the first semiconductor region and the memory arranged outside the pads are coupled to a bus interface unit via separate memory buses and a selector. The selector is driven by two phase, non-overlapping clock signals. A semiconductor integrated circuit device is provided that can easily accommodate for modification in the memory capacity of the memory and that can transfer signal/data at high speed with a low power consumption, irrespective of modification in bus interconnection length.

Abstract: A semiconductor chip is divided into a first semiconductor region surrounded by pads and a region outside the pads. A memory is arranged at the region outside the pads. A memory arranged in the first semiconductor region and the memory arranged outside the pads are coupled to a bus interface unit via separate memory buses and a selector. The selector is driven by two phase, non-overlapping clock signals. A semiconductor integrated circuit device is provided that can easily accommodate for modification in the memory capacity of the memory and that can transfer signal/data at high speed with a low power consumption, irrespective of modification in bus interconnection length.

Abstract: It is an object to prevent peak power consumption occurring on transition from normal mode to a small power consumption mode. A control-signal generating circuit (4) controls an oscillation circuit (2) and control circuits (3A) and (3B) to realize three types of clock modes including the normal mode in which both of clocks (MC) and (PC) are supplied, a wait mode as a small power consumption mode in which only the clock (PC) is supplied and a stop mode as another small power consumption mode in which supply of both of the clocks (MC) and (PC) is interrupted. Control input signals (EI) and (SI) for instructing to control the control-signal generating circuit (4) are not allowed to pass through a CPU (5) and directly supplied from an ICU (6) in response to the external request signals (ERA) and (ERB). Since the transition to the small power consumption mode does not require the operation of the CPU (5), the peak power consumption can be prevented.

Abstract: A microcomputer module 21 and a memory module 31 are mounted on a mounting substrate 42 in such a manner that first outer leads 23 of the microcomputer module 21 and first outer leads 33 of the memory module 31 are connected together in an overlapped manner.

Abstract: An access condition coincidence detecting circuit detects that an address stored in an access condition storing register 44 is outputted to an address bus 29. When a counter 46 counts a certain number of detecting signals, it inputs a break point signal to an AND circuit 36. On the other hand, it is detected that an address stored in a break address storing register 34 is outputted to the address bus 29. When the break point signal is inputted to the AND circuit 36, this detecting signal is outputted from the AND circuit 36 as an interruption demand signal. Such a construction provides an emulation apparatus capable of securely controlling interruption of a program under complicated address coincidence conditions in an emulating operation of a microcomputer.

Abstract: A pharmaceutical composition containing as the essential active ingredient a benzofuran derivative of the formula: ##STR1## wherein A is --COR', ##STR2## or ethyl group; B is hydrogen atom when A is --COR' ##STR3## or --COR" substituted at the 3 or 4 position of the benzofuran nucleus when A is ethyl; R is an alkyl group having 1 to 5 carbon atoms; R' is an alkyl group having 1 to 4 carbon atoms, an alkoxy group having 1 to 3 carbon atoms or phenyl group; R" is an alkyl group having 1 to 4 carbon atoms, phenyl or phenylalkyl group wherein the alkyl moiety has 1 to 2 carbon atoms; and the substituted propoxy group is at the 3, 4, 5, 6 or 7 position of the benzofuran nucleus; or a pharmaceutically acceptable acid addition salt thereof in admixture with a pharmaceutically acceptable carrier. The pharmaceutical composition possesses a superior .beta.-adrenergic blocking activity and local anesthetic activity, and is useful for the prevention and treatment of heart diseases, hypertension and hyperthyroidism.