Abstract: A data transfer control unit located between a memory unit and at least one peripheral unit comprises a buffer having a plurality of addressable storage locations, and first and second control circuits. In response to a request command given from the peripheral unit, the first control circuit generates an identification number and sends the request command and the identification number to the memory unit. The memory unit outputs to the data transfer control unit the identification number given together with the request command from the first control circuit, after performing a processing requested by the request command. The second control circuit stores the identification number given from the memory unit at a storage location in the buffer. The control unit further comprises a comparator which compares the identification number with the address of the storage location in the buffer at which the identification number is stored.