Patents by Inventor Masahiko Nakajikkoku
Masahiko Nakajikkoku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7782123Abstract: A semiconductor integrated circuit provided with: a transistor M7 with a control terminal supplied with a second voltage GND, a first terminal connected to a third node N3, and second terminal connected to a fourth node N4 for introducing current according to the potential at a second voltage supply node N8, the transistor M7 having a specific value for a threshold value representing the size of voltage supplied to the control terminal to conduct a current of a specific amount between the first terminal and the second terminal; and a transistor M5 with a control terminal connected to fourth node N4, first terminal supplied with a first voltage, and a second terminal connected to a second node N2, the threshold value of transistor M5 being smaller than the specific value.Type: GrantFiled: December 2, 2008Date of Patent: August 24, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Masahiko Nakajikkoku
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Publication number: 20090146733Abstract: A semiconductor integrated circuit provided with: a transistor M7 with a control terminal supplied with a second voltage GND, a first terminal connected to a third node N3, and second terminal connected to a fourth node N4 for introducing current according to the potential at a second voltage supply node N8, the transistor M7 having a specific value for a threshold value representing the size of voltage supplied to the control terminal to conduct a current of a specific amount between the first terminal and the second terminal; and a transistor M5 with a control terminal connected to fourth node N4, first terminal supplied with a first voltage, and a second terminal connected to a second node N2, the threshold value of transistor M5 being smaller than the specific value.Type: ApplicationFiled: December 2, 2008Publication date: June 11, 2009Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Masahiko NAKAJIKKOKU
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Patent number: 7545128Abstract: With the objective of reducing current consumption of a regulator circuit per se, switches for performing on/off of an operating current are inserted in series with transistors of a reference voltage generating unit and a differential amplifying unit that constitute the regulator circuit. A switch for turning on/off an electrical connection between the reference voltage generating unit and the differential amplifying unit is provided. These switches are periodically on/off-controlled in accordance with a clock signal. Incidentally, when the timing provided to turn on the switch is made faster than the timings provided to turn on the remaining switches, the operation of the differential amplifying unit can be further stabilized.Type: GrantFiled: May 25, 2007Date of Patent: June 9, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Masahiko Nakajikkoku
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Publication number: 20070290751Abstract: With the objective of reducing current consumption of a regulator circuit per se, switches for performing on/off of an operating current are inserted in series with transistors of a reference voltage generating unit and a differential amplifying unit that constitute the regulator circuit. A switch for turning on/off an electrical connection between the reference voltage generating unit and the differential amplifying unit is provided. These switches are periodically on/off-controlled in accordance with a clock signal. Incidentally, when the timing provided to turn on the switch is made faster than the timings provided to turn on the remaining switches, the operation of the differential amplifying unit can be further stabilized.Type: ApplicationFiled: May 25, 2007Publication date: December 20, 2007Applicant: OKI ELECTRIC INDUSTRY CO., LTD.Inventor: Masahiko Nakajikkoku
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Patent number: 6600361Abstract: A semiconductor device comprises a first current mirror circuit (101) which has an input terminal (101I) and an output terminal (101O), a second current mirror circuit (102) which has an input terminal (102I) and an output terminal (102O) wherein the input terminal (102I) is coupled with the output terminal (101O) wherein the output terminal (102O) is coupled with said input terminal (101I) and a start-up circuit (103) which supplies current to input terminal (102I) based on voltage on the input terminal (101I).Type: GrantFiled: October 16, 2001Date of Patent: July 29, 2003Assignee: Oki Electric Industry Co., Ltd.Inventors: Masafumi Nagaya, Masahiko Nakajikkoku
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Patent number: 6586975Abstract: A semiconductor device has a start-up circuit which comprises a third node (N3), a first switch (103A) which electrically connects a first node (N1) and an input terminal (102I) of a second mirror circuit (102) based on a voltage level at the third node; a second switch (103B) which electrically connects the first node and the third node based on a voltage level at an input terminal (101I) of a first current mirror circuit (101); and a third switch (103C) which electrically connects the first node and the third node based on an inverted voltage level at the third node.Type: GrantFiled: October 16, 2001Date of Patent: July 1, 2003Assignee: Oki Electric Industry, Co., Ltd.Inventors: Masafumi Nagaya, Masahiko Nakajikkoku
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Publication number: 20030098728Abstract: A semiconductor device comprises a first current mirror circuit (101) which has an input terminal (101I) and an output terminal (101O), a second current mirror circuit (102) which has an input terminal (102I) and an output terminal (102O) wherein the input terminal (102I) is coupled with the output terminal (101O) wherein the output terminal (102O) is coupled with said input terminal (101I) and a start-up circuit (103) which supplies current to input terminal (102I) based on voltage on the input terminal (101I).Type: ApplicationFiled: January 9, 2003Publication date: May 29, 2003Inventors: Masafumi Nagaya, Masahiko Nakajikkoku
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Publication number: 20020050855Abstract: A semiconductor device has a start-up circuit which comprises a third node (N3), a first switch (103A) which electrically connects a first node (N1) and an input terminal (102I) of a second mirror circuit (102) based on a voltage level at the third node; a second switch (103B) which electrically connects the first node and the third node based on a voltage level at an input terminal (101I) of a first current mirror circuit (101); and a third switch (103C) which electrically connects the first node and the third node based on an inverted voltage level at the third node.Type: ApplicationFiled: October 16, 2001Publication date: May 2, 2002Inventors: Masafumi Nagaya, Masahiko Nakajikkoku
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Publication number: 20020051390Abstract: A semiconductor device comprises a first current mirror circuit (101) which has an input terminal (101I) and an output terminal (101O), a second current mirror circuit (102) which has an input terminal (102I) and an output terminal (102O) wherein the input terminal (102I) is coupled with the output terminal (101O) wherein the output terminal (102O) is coupled with said input terminal (101I) and a start-up circuit (103) which supplies current to input terminal (102I) based on voltage on the input terminal (101I).Type: ApplicationFiled: October 16, 2001Publication date: May 2, 2002Inventors: Masafumi Nagaya, Masahiko Nakajikkoku