Patents by Inventor Masahiko Nishiuma

Masahiko Nishiuma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5616520
    Abstract: A semiconductor device is fabricated by forming first metal balls on electrode pads of a semiconductor chip. The first metal balls each can have a sharp tipped anchor. All of the anchors simultaneously flattened slightly only to the extent of equalizing the height thereof. The first metal balls are bonded to electrodes formed on a substrate with wirings by embedding the anchors into the electrodes. Alternatively, second metal balls can be formed on the electrodes which are then flattened to equalize the height thereof. The first metal balls, either with or without the anchors, are bonded to the second metal balls. The first and second metal balls are preferably heated during the bonding step to soften the second metal balls.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: April 1, 1997
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Masahiko Nishiuma, Norio Nakazato, Hiroyuki Takahashi, Chiyoshi Kamada, Motoo Suwa
  • Patent number: 5523622
    Abstract: For taking a characteristic impedance matching of signal transmission lines in a package which carries thereon a semiconductor chip with a very high-speed LSI formed thereon, there is provided a semiconductor integrated circuit device wherein one ends of signal transmission lines formed on a main surface of a package substrate are extended up to the position just under pads formed on a main surface of the semiconductor chip and are connected to the pads on the chip electrically through bump electrodes, while opposite ends of the signal transmission lines are extended to the outer peripheral portion of the main surface of the package substrate and outer leads are bonded thereto.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: June 4, 1996
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Takashi Harada, Kazuhiro Yoshihara, Kazutaka Masuzawa, Kiyoshi Hayashi, Jun Kumazawa, Kenji Nagai, Masahiko Nishiuma, Chiyoshi Kamada
  • Patent number: 5225709
    Abstract: A packaged semiconductor device has a package, a semiconductor IC chip disposed in a space formed in the package, a strip conductor buried at a first level in the package for carrying a signal to be coupled to the IC chip, a first reference potential conductor buried at a second level in the package for providing a reference potential for the IC chip and a second reference potential conductor buried at the first level in the package for shielding the strip conductor. A connection conductor such as a bonding wire is provided across the second reference potential conductor for connecting the IC chip with one of the ends of the strip conductor. A dielectric material is provided between the connection conductor and the second reference potential conductor to provide the connection conductor with a characteristic impedance matched with an impedance of a source of the signal the connection conductor carries.
    Type: Grant
    Filed: June 13, 1991
    Date of Patent: July 6, 1993
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Masahiko Nishiuma, Chiyoshi Kamada