Abstract: Disclosed herein is a semiconductor device including a conductive member that has a main surface facing in a thickness direction, a semiconductor element that has a plurality of pads facing the main surface, a plurality of electrodes that are individually formed with respect to the plurality of pads and protrude from the plurality of pads toward the main surface, and a bonding layer for electrically bonding the main surface to the plurality of electrodes. The bonding layer includes a first region having conductivity and a second region having electrical insulation. The first region includes a metal portion. At least a part of the second region includes a resin portion.

Abstract: Provided is a method for efficiently manufacturing high-purity peripheral nerve cells from undifferentiated cells. The method for manufacturing peripheral nerve cells from undifferentiated cells having an ability to differentiate into peripheral nerve cells includes the following steps (a) and (b): (a) culturing undifferentiated cells having an ability to differentiate into peripheral nerve cells to induce differentiation into neural progenitor cells without detaching a grown colony from a culture vessel; and (b) detaching the neural progenitor cells produced in the step (a) from the culture vessel, then seeding the cells at a seeding density of 2×105 to 6×105 cells/cm2 to a culture vessel, and culturing the cells for 14 to 42 days.

Abstract: Provided is a method for efficiently manufacturing high-purity peripheral nerve cells from undifferentiated cells. The method for manufacturing peripheral nerve cells from undifferentiated cells having an ability to differentiate into peripheral nerve cells includes the following steps (a) and (b): (a) culturing undifferentiated cells having an ability to differentiate into peripheral nerve cells to induce differentiation into neural progenitor cells without detaching a grown colony from a culture vessel; and (b) detaching the neural progenitor cells produced in the step (a) from the culture vessel, then seeding the cells at a seeding density of 2×105 to 6×105 cells/cm2 to a culture vessel, and culturing the cells for 14 to 42 days.

Abstract: To provide a method for determining the sensitivity of a patient to irinotecan, SN-38, and/or a salt thereof, which method can determine the therapeutic response of the patient and to provide a novel cancer therapeutic means employing the method. The method for determining the sensitivity of a subject to irinotecan, SN-38, and/or a salt thereof includes measuring the expression levels of AMD1 gene, CTSC gene, EIF1AX gene, C12orf30 gene, DDX54 gene, PTPN2 gene, and TBX3 gene in a specimen, and calculating the best tumor response rate (%), overall survival (days), or progression-free survival (days) from formulas (1) to (3).

Abstract: To provide a marker for determining sensitivity of a patient to an anti-cancer agent, which marker can determine whether or not the patient has a therapeutic response to the anti-cancer agent, and novel cancer therapeutic means employing the marker. The marker for determining the sensitivity of a subject to an anti-cancer agent including oxaliplatin or a salt thereof, fluorouracil or a salt thereof, and levofolinate or a salt thereof, the marker containing one or more genes selected from the group consisting of ALAD gene, C20orf43 gene, CABLES1 gene, CDC14B gene, GDA gene, HOXB6 gene, RPL7AP27 gene, TMEM18 gene, and UGT2B10 gene.

Abstract: A semiconductor device that makes isolation circuits unnecessary and that also resolves the problem of through-current flowing during power supply shutdown transitions and during power supply recovery and that even flows between the regions during power shutdown. A semiconductor device of the present invention including a first power supply line, and a second power supply line coupled to a first power supply line by way of a first switch, a macro cell containing a macro cell core coupled to the second power supply line, and a third power supply line coupled by way of a second switch to a first power supply line, and a circuit block coupled to the third power supply line and also coupled to at least either the macro cell core input or output; and the second power supply line is coupled to the third power supply line.

Abstract: A semiconductor device having an SRAM macro which has a power-off function and facilitates a design associated with a change in storage capacity is provided. The semiconductor device has plural layout units each including a memory array having plural memory cells in an SRAM, a first peripheral circuit that writes data into the memory array and reads the data from the memory array, and a switch group that disconnects the memory array and the first peripheral circuit, and power wires.

Abstract: To provide a marker for determining sensitivity of a patient to an anti-cancer agent, which marker can determine whether or not the patient has a therapeutic response to the anti-cancer agent, and novel cancer therapeutic means employing the marker. The marker for determining the sensitivity of a subject to an anti-cancer agent including oxaliplatin or a salt thereof, fluorouracil or a salt thereof, and levofolinate or a salt thereof, the marker containing one or more genes selected from the group consisting of ALAD gene, C20orf43 gene, CABLES1 gene, CDC14B gene, GDA gene, HOXB6 gene, RPL7AP27 gene, TMEM18 gene, and UGT2B10 gene.

Abstract: A semiconductor device having an SRAM macro which has a power-off function and facilitates a design associated with a change in storage capacity is provided. The semiconductor device has plural layout units each including a memory array having plural memory cells in an SRAM, a first peripheral circuit that writes data into the memory array and reads the data from the memory array, and a switch group that disconnects the memory array and the first peripheral circuit, and power wires.

Abstract: A semiconductor device that makes isolation circuits unnecessary and that also resolves the problem of through-current flowing during power supply shutdown transitions and during power supply recovery and that even flows between the regions during power shutdown. A semiconductor device of the present invention including a first power supply line, and a second power supply line coupled to a first power supply line by way of a first switch, a macro cell containing a macro cell core coupled to the second power supply line, and a third power supply line coupled by way of a second switch to a first power supply line, and a circuit block coupled to the third power supply line and also coupled to at least either the macro cell core input or output; and the second power supply line is coupled to the third power supply line.

Abstract: To provide a method for determining the sensitivity of a patient to irinotecan, SN-38, and/or a salt thereof, which method can determine the therapeutic response of the patient and to provide a novel cancer therapeutic means employing the method. The method for determining the sensitivity of a subject to irinotecan, SN-38, and/or a salt thereof includes measuring the expression levels of AMD1 gene, CTSC gene, EIF1AX gene, C12orf30 gene, DDX54 gene, PTPN2 gene, and TBX3 gene in a specimen, and calculating the best tumor response rate (%), overall survival (days), or progression-free survival (days) from formulas (1) to (3).

Abstract: The present invention provides a gene related to cancer cell immortalization (an immortalization determining gene) and a process that is useful for selective cancer treatment targeting a cancer cell having the gene. The present invention determines an immortalized cancer cell using a polynucleotide having a base sequence of at least 15 bases that specifically hybridizes with a continuous base sequence of at least 15 bases within any one of abase sequences represented by SEQ ID Nos. 1 to 13. In the foregoing process, the polynucleotide is used as a primer or probe for detecting an immortalization determining gene that exhibits high expression specifically in an immortalized cancer cell.

Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.

Abstract: In relation to the built-in self-test circuit (BIST circuit) for testing CAM macros, the present invention is intended to provide a means to enable reduction in amount of materials as required for wiring channel region for signal distribution, buffer, FF, etc., and in number of LSI pins, and further, to facilitate mounting on chips. The data generators for CAM testing, inserted between the APG for RAMs and CAM macros, create data to write to the CAM macros by obtaining the address signals directly or by decoding the same signals. The APG is common to all the memory macros, and testing proper to each CAM can be carried out by changing over the operation of the inserted data generators by means of the control signal. The data generators are arranged in the proximity of the CAM macros, the circuits to be tested.

Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.

Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.

Abstract: The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin.

Abstract: There is provided a control circuit (409) for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.

Abstract: The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin.

Abstract: The invention intends to provide a technique that achieves a sufficient phase margin with ease. The circuit includes a power supply circuit that is formed with a phase compensating resistor and a phase compensating capacitor, between a second input terminal of a differential amplifier and a low supply voltage. Thereby, the first pole frequency in the overall gain is determined by the first pole frequency in the voltage-dividing resistor stage in the Bode diagram for the pole/zero compensation, which is shifted to a lower frequency. Also, the zero point cancels the first pole frequency in the differential amplifier stage, which reduces the phase delay to secure the phase margin.