Patents by Inventor Masahiko Saito

Masahiko Saito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9381117
    Abstract: Provided is a medical knife which makes it possible to maintain low penetration resistance, without the maximum-width parts of the medical knife creating sudden changes in penetration resistance even when passing through tissue. A knife comprises: a pointed tip; a cutting part which has edges consisting of first oblique faces which are formed along the outer periphery and second oblique faces which are formed inside the first oblique faces; maximum-width parts; and a shank part which is formed contiguously with the maximum-width parts. The cutting part is formed in such a way that the shape of the planar projection thereof becomes wider from the pointed tip towards the maximum-width parts, and the first oblique faces extend further towards the shank part side than the second oblique faces over at least one portion of the area running from the maximum-width parts to the shank part.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: July 5, 2016
    Assignee: MANI, Inc.
    Inventor: Masahiko Saito
  • Patent number: 9304789
    Abstract: A pseudo task generation requester 200 generates a request for generating a pseudo task 283 indicating that a certain one of CPUs is in an use state, and notifies a second OS 125 of the generation request, in the case where a task to be processed by a first virtual machine 110 is assigned to the one CPU, but a task to be processed by a second virtual machine 120 is not assigned to the one CPU. A pseudo task finishing requester 206 finishes the pseudo task 283 when a task in the first virtual machine 110 is finished with respect to the CPU to which the pseudo task 283 is assigned.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: April 5, 2016
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Kazuomi Kato, Masahiko Saito
  • Publication number: 20160046808
    Abstract: Polymer composition comprising an aromatic polyamide, more than 5 wt. % (based on the total weight of the composition) of at least one crystalline silicate chosen from nesosilicates, sorosilicates, cyclosilicates, tectosilicates and inosilicates, more than 2 wt. % (based on the total weight of the composition) of at least one white pigment, and/or more than 0.003 wt. % (based on the total weight of the composition) of at least one optical brightener, and more than 1 wt. % (based on the total weight of the composition) of at least one optionally functionalized olefin copolymer.
    Type: Application
    Filed: October 29, 2015
    Publication date: February 18, 2016
    Inventors: Christie W. CROWE, Masahiko SAITO
  • Patent number: 9218287
    Abstract: A virtual machine system comprises: a processor for executing a secure operating system and a normal operating system; and a cache memory. The cache memory stores data in a manner that allows for identification of whether the data has been read from a secure storage area of an external main memory. The cache memory writes back data to the main memory in a manner that reduces the number of times data is intermittently written back to the secure storage area which occurs when the processor is executing the normal operating system.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: December 22, 2015
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Ryota Miyazaki, Masahiko Saito
  • Patent number: 9170832
    Abstract: A virtual machine control apparatus 100 controls execution of a first type virtual machine A210 and a second type virtual machine 220. The first type virtual machine A210 includes a start detection unit 261 which detects an operation in the first type virtual machine A210 to start usage of a device (external storage device 160). The first type virtual machine A210 also includes a start signal output unit 262 which outputs a start signal when the start detection unit 261 detects the operation to start usage of the device. The second type virtual machine 220 includes a control unit (external storage device driver 272) which, when the start signal output unit 262 outputs the start signal while the device is in set in a low power mode (electrical power set to off), sets the device in a normal mode (electrical power set to on).
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: October 27, 2015
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Katsushige Amano, Masahiko Saito, Tadao Tanikawa, Takuya Kondoh, Toshiaki Takeuchi
  • Patent number: 9132036
    Abstract: [Problems] To ensure the sharpness of a stripping knife whereby a part of a living tissue is incised and stripped while preventing a cut along the thickness direction. [Means for Solving Problems] A stripping knife (A) having a plate-shaped blade (3) having an edge (1) around the periphery, a shank (5) connected to the blade (3), and a handle (7) holding the shank (5) in the integrated state, wherein the blade (3) is composed of the edge (1) formed at the front end and a guide face (2) which is formed between the edge (1) and the front face (3b) of the connected plate constituting the blade (3) and brought into contact with the surface (13) of the remaining tissue.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: September 15, 2015
    Assignee: MANI, INC.
    Inventors: Akio Yamaguchi, Masatoshi Fukuda, Masahiko Saito
  • Publication number: 20150248742
    Abstract: A graphics display processing device including: a graphics processor that executes GPU instructions based on a primary drawing instruction and a secondary drawing instruction; an acquirer) that acquires the primary drawing instruction and the secondary drawing instruction; an estimator that calculates an estimated GPU processing time required for executing the GPU instructions; a determiner that determines, using the estimated GPU processing time, which of the primary drawing instruction and the secondary drawing instruction is to be executed first; an issuance controller that performs a control when the primary drawing instruction is to be executed first, causing the primary drawing instruction to be issued and issuance of the secondary drawing instruction to be postponed; an instruction issuer that issues each drawing instruction according to the control of the issuance controller; and a graphics driver that generates the GPU instructions by executing each drawing instruction issued.
    Type: Application
    Filed: May 22, 2014
    Publication date: September 3, 2015
    Applicant: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Tetsuji Yamamoto, Masahiko Saito, Takuya Kondoh
  • Publication number: 20150197635
    Abstract: Polymer composition comprising an aromatic polyamide, more than 5 wt. % (based on the total weight of the composition) of at least one crystalline silicate chosen from nesosilicates, sorosilicates, cyclosilicates, tectosilicates and inosilicates, more than 2 wt. % (based on the total weight of the composition) of at least one white pigment, and/or more than 0.003 wt. % (based on the total weight of the composition) of at least one optical brightener, and more than 1 wt. % (based on the total weight of the composition) of at least one optionally functionalized olefin copolymer.
    Type: Application
    Filed: January 3, 2014
    Publication date: July 16, 2015
    Applicant: SOLVAY ADVANCE POLYMERS, L.L.C.
    Inventors: Christie W. Crowe, Masahiko Saito
  • Patent number: 9069589
    Abstract: The present invention relates to a virtual machine system that includes a plurality of processors and executes a plurality of virtual machines in parallel with use of the plurality of processors. An aim thereof is to suppress power consumption without sacrificing the performance of the virtual machine system. When there are at least two processors that do not have any virtual machines allocated thereto, one of the at least two processors is supplied with power so as to be placed in a standby state, and a remaining one or more of the at least two processors are not supplied with power.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: June 30, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Masahiko Saito, Ryota Miyazaki, Tadao Tanikawa, Katsushige Amano, Masashi Sugiyama
  • Patent number: 9063868
    Abstract: A virtual computer system having a plurality of virtual computers includes an area assignment unit operable to, when a virtual computer attempts to perform writing to a basic area which is assigned to and shared by the plurality of virtual computers, change an assignment to the virtual computer from the basic area to a copy area to which the basic area is copied and the writing is performed. Additionally an area freeing unit is operable to, when a content of the basic area matches a content of at least one copy area, change area assignment to one or more virtual computers, to which have been assigned one or more other areas than one area among the areas whose contents match each other, to the one area, and free the one or more other areas.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: June 23, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventor: Masahiko Saito
  • Patent number: 9032407
    Abstract: In a multiprocessor system, in general, a processor assigned with a larger amount of tasks is apt to perform a larger amount of communication with other processors assigned with tasks, than a processor assigned with a smaller amount of tasks. Thus in order for each processor to be able to perform the routing process efficiently, tasks are assigned such that, when there are a first processor and a second processor, the number of processors each assigned with one or more tasks and directly connected with the second processor being smaller than the number of processors each assigned with one or more tasks and directly connected with the first processor, the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: May 12, 2015
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventor: Masahiko Saito
  • Patent number: 9032401
    Abstract: When a process judging unit judges that a target process is a protected process, a key judging unit judges whether a target key that is a key generated by a key generating unit is a first key or a second key. When the key judging unit judges that the target key is the first key, a VM communication managing unit notifies the target process of a memory ID of a protected memory region corresponding to the first key. When the process judging unit judges that the target process is an unprotected process, a key transforming unit transforms the target key from the first key to the second key based on the key transformation rule. An HV communication managing unit notifies the target process of a memory ID of an unprotected memory region corresponding to the second key.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 12, 2015
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Teruo Kamiyama, Katsushige Amano, Masahiko Saito, Tadao Tanikawa
  • Patent number: 8918664
    Abstract: An integrated circuit provided with a processor includes a loop detection unit that detects execution of a loop in the processor, a loop-carried dependence analysis unit that analyzes the loop in order to detect loop-carried dependence, and a power control unit that performs power saving control when no loop-carried dependence is detected. By detecting whether a loop has loop-carried dependence, loops for calculation or the like can be excluded from power saving control. As a result, a larger variety of busy-waits can be detected, and the amount of power wasted by a busy-wait can be reduced.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: December 23, 2014
    Assignee: Panasonic Corporation
    Inventors: Masashi Sugiyama, Masahiko Saito
  • Patent number: 8898666
    Abstract: A virtual machine system is provided with a processor having only two privileged modes, a low privileged mode and a high privileged mode, and achieves both a security function for protecting digital copyrighted works or the like and an operating system switching function that guarantees system reliability. The virtual machine system is provided with a first and a second processor and executes a hypervisor on the first processor in the high privileged mode. An operating system on the second processor is executed by cooperation between the hypervisor running on the first processor and a program running on the second processor in low privileged mode. This eliminates the need for running the hypervisor on the second processor in the high privileged mode, thus allowing for execution on the second processor in the high privileged mode of a program for implementing the security function.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: November 25, 2014
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Masahiko Saito, Teruto Hirota, Hiroo Ishikawa
  • Patent number: 8881265
    Abstract: A computer system includes a memory having a secure area and a plurality of processors using the memory. When an access-allowed program unit executed by one of the processors starts an access to the secure area, the program unit subject to execution by the other processors is limited to the access-allowed program unit.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: November 4, 2014
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Hiroo Ishikawa, Masahiko Saito
  • Patent number: 8826958
    Abstract: A crimping die including a fixed die and a moving die which moves away from or toward the fixed die, and a thread guide arranged closely to the edge of the stop hole formed in the proximal end face of an eyeless needle held by the crimping die and having a surface for guiding the suture thread to the stop hole. The thread guide is arranged such that an external force does not act on the suture thread on the outside of the stop hole formed in the eyeless needle as a crimping operation progresses when the proximal end face of the eyeless needle is crimped by the crimping die, or arranged to move in the direction in which an external force does not act.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: September 9, 2014
    Assignee: MANI, Inc.
    Inventors: Kanji Matsutani, Masahiko Saito
  • Publication number: 20140196034
    Abstract: A virtual machine control apparatus 100 controls execution of a first type virtual machine A210 and a second type virtual machine 220. The first type virtual machine A210 includes a start detection unit 261 which detects an operation in the first type virtual machine A210 to start usage of a device (external storage device 160). The first type virtual machine A210 also includes a start signal output unit 262 which outputs a start signal when the start detection unit 261 detects the operation to start usage of the device. The second type virtual machine 220 includes a control unit (external storage device driver 272) which, when the start signal output unit 262 outputs the start signal while the device is in set in a low power mode (electrical power set to off), sets the device in a normal mode (electrical power set to on).
    Type: Application
    Filed: January 25, 2013
    Publication date: July 10, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Katsushige Amano, Masahiko Saito, Tadao Tanikawa, Takuya Kondoh, Toshiaki Takeuchi
  • Publication number: 20140020086
    Abstract: A virtual machine system that restricts use of confidential information only to the case where an authentication has resulted in success. The virtual machine system includes first virtual machine, second virtual machine, and hypervisor. The first virtual machine includes: storage unit storing confidential information; and authentication unit configured to perform authentication and notify the hypervisor of result of the authentication. The second virtual machine uses virtual device that is virtualized storage device. When having received authentication result indicating authentication success from the authentication unit, the hypervisor enables the second virtual machine to access, as substance of the virtual device, storage area storing the confidential information, and when not having received the authentication result indicating the authentication success from the authentication unit, the hypervisor disables the second virtual machine from accessing the storage area storing the confidential information.
    Type: Application
    Filed: February 20, 2013
    Publication date: January 16, 2014
    Applicant: Panasonic Corporation
    Inventors: Tadao Tanikawa, Masahiko Saito, Katsushige Amano, Toshiaki Takeuchi
  • Publication number: 20130232493
    Abstract: A pseudo task generation requester 200 generates a request for generating a pseudo task 283 indicating that a certain one of CPUs is in an use state, and notifies a second OS 125 of the generation request, in the case where a task to be processed by a first virtual machine 110 is assigned to the one CPU, but a task to be processed by a second virtual machine 120 is not assigned to the one CPU. A pseudo task finishing requester 206 finishes the pseudo task 283 when a task in the first virtual machine 110 is finished with respect to the CPU to which the pseudo task 283 is assigned.
    Type: Application
    Filed: August 3, 2012
    Publication date: September 5, 2013
    Inventors: Kazuomi Kato, Masahiko Saito
  • Publication number: 20130191617
    Abstract: A computer system includes a memory having a secure area and a plurality of processors using the memory. When an access-allowed program unit executed by one of the processors starts an access to the secure area, the program unit subject to execution by the other processors is limited to the access-allowed program unit.
    Type: Application
    Filed: July 20, 2012
    Publication date: July 25, 2013
    Inventors: Hiroo Ishikawa, Masahiko Saito