Patents by Inventor Masahiko Takeuchi
Masahiko Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120211836Abstract: To prevent contact plugs formed to sandwich an abutting portion between gate electrodes, from being short-circuited via a void formed inside an insulating film of the abutting portion. Over sidewalls SW facing each other in the abutting portion between gate electrodes G2 and G5, a liner insulating film 6 and an interlayer insulating film 7 are formed. Between the sidewalls SW, the liner insulating film 6 formed on each of the side walls of the sidewalls SW are brought in contact with each other to close a space between the sidewalls SW to prevent a void from being generated inside the interlayer insulating film 7 and the liner insulating film 6.Type: ApplicationFiled: February 7, 2012Publication date: August 23, 2012Inventor: Masahiko TAKEUCHI
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Patent number: 8120116Abstract: Shared contact holes SC1 and SC2 reach both gate electrode layers GE1 and GE2 and a drain region PIR. In a planar view, a sidewall E2 of gate electrode layers GE1 and GE2 is shifted toward a side of a sidewall E4 from a virtual extended line E1a of the sidewall E1. In a planar view, a center line of a line width D1 in a portion that shared contact holes SC1 and SC2 of gate electrode layers GE1 and GE2 reach is located while shifted with respect to a center line of a line width D2 in a portion located on channel formation regions CHN1 and CHN2 of gate electrode layers GE1 and GE2. Therefore, a semiconductor device and a photomask that can suppress an opening defect of the shared contact hole are obtained.Type: GrantFiled: December 22, 2008Date of Patent: February 21, 2012Assignee: Renesas Electronics CorporationInventor: Masahiko Takeuchi
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Publication number: 20110099987Abstract: An exhaust gas purification catalyst includes: a lower catalyst layer that contains a ceria-zirconia mixed oxide having 50 to 70 mass % of CeO2 and 5 mass % or more of Pr2O3 and carries at least one of Pt and Pd; and an upper catalyst layer that contains at least zirconia and carries at least Rh, wherein the total amount of CeO2 per liter of the carrier base is 15 to 30 g. Because the amount of CeO2 is small, formation of H2S is suppressed and a high capability of adsorbing and releasing oxygen is brought out in spite of the small amount of CeO2.Type: ApplicationFiled: June 26, 2009Publication date: May 5, 2011Inventors: Akemi Satou, Masahiko Takeuchi, Keizo Hiraku, Yusuki Kawamura, Takahiro Fujiwara, Tadashi Suzuki, Naoki Takahashi
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Publication number: 20110101461Abstract: The present invention presupposes a MIPS electrode in which a gate electrode of a MISFET is made up of a stacked film of a metal film and a polysilicon film. Then, by a first characteristic point that a gate contact hole is formed to have an opening diameter larger than a gate length of the gate electrode of the MIPS electrode and a second characteristic point that a concave portion is formed in a side surface of the metal film constituting the gate electrode, the further reduction of the gate resistance (parasitic resistance) and the improvement of the connection reliability between the gate electrode and the gate plug can be achieved.Type: ApplicationFiled: October 29, 2010Publication date: May 5, 2011Inventors: Masahiko TAKEUCHI, Ryo NAKAGAWA, Kazuo NAKAGAWA
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Patent number: 7763926Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).Type: GrantFiled: October 7, 2008Date of Patent: July 27, 2010Assignee: Renesas Technology Corp.Inventor: Masahiko Takeuchi
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Publication number: 20090166745Abstract: Shared contact holes SC1 and SC2 reach both gate electrode layers GE1 and GE2 and a drain region PIR. In a planar view, a sidewall E2 of gate electrode layers GE1 and GE2 is shifted toward a side of a sidewall E4 from a virtual extended line E1a of the sidewall E1. In a planar view, a center line of a line width D1 in a portion that shared contact holes SC1 and SC2 of gate electrode layers GE1 and GE2 reach is located while shifted with respect to a center line of a line width D2 in a portion located on channel formation regions CHN1 and CHN2 of gate electrode layers GE1 and GE2. Therefore, a semiconductor device and a photomask that can suppress an opening defect of the shared contact hole are obtained.Type: ApplicationFiled: December 22, 2008Publication date: July 2, 2009Inventor: Masahiko TAKEUCHI
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Publication number: 20090032857Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).Type: ApplicationFiled: October 7, 2008Publication date: February 5, 2009Applicant: Renesas Technology Corp.Inventor: Masahiko TAKEUCHI
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Patent number: 7439569Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).Type: GrantFiled: June 20, 2006Date of Patent: October 21, 2008Assignee: Renesas Technology Corp.Inventor: Masahiko Takeuchi
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Patent number: 7363858Abstract: A printing apparatus includes a printing plate feeder for feeding printing plates to a first plate cylinder. The printing plate feeder has a pair of transport rollers acting as a leveling roller and a driven roller. The leveling roller is fixed to a leveling roller rotary shaft extending parallel to a rotational axis of the first plate cylinder, and is opposed to middle and opposite end regions of the first plate cylinder. The leveling roller rotary shaft is connected to a driving device, a one-way clutch for permitting rotation only in a transport direction of the printing plates, and a torque transmission clutch acting as a loading device for applying a load to rotation in a direction opposite to the transport direction of the printing plates.Type: GrantFiled: March 15, 2005Date of Patent: April 29, 2008Assignee: Dainippon Screen Mfg. Co., Ltd.Inventors: Kenji Edamitsu, Masahiko Takeuchi
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Publication number: 20080057299Abstract: The present invention aims to provide a polyimide resin excellent in heat resistance, dimensional stability, and toughness as an insulating layer, and to obtain a laminate suitable for a flexible wiring board by using the polyimide resin, the laminate being excellent in resistance to rupture and flexibility even when the thickness of a polyimide resin layer is small. Provided is a laminate for a wiring board having a metal layer on at least one surface of a polyimide resin layer, in which a polyimide resin layer (A) obtained by imidating a polyimide precursor resin having a weight average molecular weight of 150,000 to 800,000 is a main polyimide resin layer, and a polyimide resin of which the main polyimide resin layer is constituted has structural units represented by the following general formulae (1) and (2) where R represents a lower alkyl group, a phenyl group, or a halogen atom, and Ar1 represents a residue of bis(aminophenoxy)benzene or bis(aminophenoxy)naphthalene.Type: ApplicationFiled: August 10, 2007Publication date: March 6, 2008Applicant: Nippon Steel Chemical Co., Ltd.Inventors: Yasuhiro Adachi, Hironori Nagaoka, Hongyuan Wang, Naoko Osawa, Masahiko Takeuchi, Hironobu Kawasato
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Publication number: 20060237759Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).Type: ApplicationFiled: June 20, 2006Publication date: October 26, 2006Applicant: Renesas Technology Corp.Inventor: Masahiko Takeuchi
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Patent number: 7078759Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).Type: GrantFiled: June 24, 2005Date of Patent: July 18, 2006Assignee: Renesas Technology Corp.Inventor: Masahiko Takeuchi
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Publication number: 20050236655Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).Type: ApplicationFiled: June 24, 2005Publication date: October 27, 2005Applicant: Renesas Technology Corp.Inventor: Masahiko Takeuchi
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Publication number: 20050229802Abstract: A printing apparatus includes a printing plate feeder for feeding printing plates to a first plate cylinder. The printing plate feeder has a pair of transport rollers acting as a leveling roller and a driven roller. The leveling roller is fixed to a leveling roller rotary shaft extending parallel to a rotational axis of the first plate cylinder, and is opposed to middle and opposite end regions of the first plate cylinder. The leveling roller rotary shaft is connected to a driving device, a one-way clutch for permitting rotation only in a transport direction of the printing plates, and a torque transmission clutch acting as a loading device for applying a load to rotation in a direction opposite to the transport direction of the printing plates.Type: ApplicationFiled: March 15, 2005Publication date: October 20, 2005Inventors: Kenji Edamitsu, Masahiko Takeuchi
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Patent number: 6924192Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).Type: GrantFiled: October 31, 2003Date of Patent: August 2, 2005Assignee: Renesas Technology Corp.Inventor: Masahiko Takeuchi
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Patent number: 6852678Abstract: An aqueous lubricant is provided which by simple application onto metal surfaces forms lubricating films required for heavy working of metals, and which contains no oil. The aqueous lubricant is prepared by suspending or dispersing a metal chelate compound in water with a surfactant or the like. The metal chelate compound has a polydentate or multidentate chelate ligand, in which at least one of the coordinating atoms is sulfur, coordinated to the coordination site of at least one metal species selected from among zinc, manganese, iron, molybdenum, tin and antimony. When applied onto metal surfaces, the aqueous lubricant forms effective lubricating films on the metal surfaces. The lubricating films contain sulfur as coordinating atoms and therefore, extreme pressure produces sulfur radicals through decomposition by tribo-chemical reactions. The sulfur radicals are highly reactive and react rapidly with the metal surface to produce metal sulfides with a lubricating effect.Type: GrantFiled: November 19, 2001Date of Patent: February 8, 2005Assignees: MEC International Corporation, Toyota Jidosha Kabushiki KaishaInventors: Heijiro Ojima, Masahiko Takeuchi, Fumio Ikesue, Noritoshi Kaskimura, Fumio Kawahara, Mitsuru Tomono
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Patent number: 6849957Abstract: A semiconductor device enabling precise and accurate measurement of an inspection mark in a simple manner is obtained. The semiconductor device includes a device forming area and a dicing line area arranged to surround the device forming area on a semiconductor substrate. In the dicing line area, first and second registration marks formed in different shots are provided, and the first and second registration marks include auxiliary marks for identifying the first and second registration marks.Type: GrantFiled: November 30, 2000Date of Patent: February 1, 2005Assignee: Renesas Technology Corp.Inventors: Masahiko Takeuchi, Koichiro Narimatsu, Atsushi Ueno
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Patent number: 6837490Abstract: A paper feeding apparatus includes a first support member for supporting a central area of a lower surface of printing paper placed on a paper tray, second support members for supporting corner areas of the lower surface of the printing paper, sensors for detecting heights of an upper surface of the printing paper placed on the paper tray, motors rotatable based on signals from the sensors, and lift screws vertically movable by the motors. The second support members are connected to the lift screws to be vertically movable therewith, respectively.Type: GrantFiled: December 4, 2002Date of Patent: January 4, 2005Assignee: Dainippon Screen Mfg. Co., Ltd.Inventors: Keisuke Hirai, Masahiko Takeuchi
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Publication number: 20040232462Abstract: A technique is provided which makes it possible to achieve both of a reduction in contact resistance in a memory device and a reduction in contact resistance in a logic device even when oxidation is performed during formation of dielectric films of capacitors. Conductive barrier layers (82) are provided in the top ends of contact plugs (83b) electrically connected to ones of source/drain regions (59). Lower electrodes (70) of capacitors (73) are formed in contact with the conductive barrier layers (82) of the contact plugs (83b) and then dielectric films (71) and upper electrodes (72) of the capacitors (73) are sequentially formed. In the logic region, contact plugs (25) are formed in an upper layer so that they are in contact respectively with contact plugs (33) electrically connected to source/drain regions (9).Type: ApplicationFiled: October 31, 2003Publication date: November 25, 2004Applicant: Renesas Technology Corp.Inventor: Masahiko Takeuchi
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Publication number: 20040235241Abstract: It is an object to obtain a method of manufacturing a semiconductor device having a capacitor capable of avoiding generation of a leakage current and an electrical short circuit between electrodes which are caused by a sharp portion of a lower electrode of the capacitor and a deterioration in a crystallinity of a dielectric film of the capacitor which is caused by a residue. A surface of a ruthenium film (7) is oxidized by a low temperature plasma oxidation process to form a ruthenium oxide film (9). Also in the case in which a part of a residue (51) exists on the surface of the ruthenium film (7), the existing residue (51) is lifted off and disappears by formation of the ruthenium oxide film (9) containing RuO4 having a high vapor pressure in a large amount. The low temperature plasma oxidation process, moreover, has an anisotropy an oxidation rate in a vertical direction is higher than that in a transverse direction.Type: ApplicationFiled: March 8, 2004Publication date: November 25, 2004Applicant: Renesas Technology Corp.Inventors: Masatoshi Anma, Masahiko Takeuchi