Abstract: A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated S101, a clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated S102. When the allocated resource connection graph includes nodes to which hardware resources having the same function are allocated, a sharing edge for controlling sharing of the nodes is added between the nodes S103. A provisional layout of the allocated resource connection graph having the sharing edge added thereto is provided S104, and the nodes of the allocated resource connection graph are shared based on the layout result S105. The sharing edge is provided with attribute or weight such as attraction or repulsion. Thus, the distance between the nodes in the layout result is controlled and the degree at which the resources are shared is controlled.

Abstract: Based on a relative comparison of respective consumed powers of cells which are subjected to a layout, separation information on cells to be separated which are to be arranged in a spaced-apart manner from each other is generated by separation information generating means, and a layout is generated by layout generating means based on this separation information. Accordingly, it is no more necessary to rearrange cells or to form a layout of the entire circuit again after generating an initial layout. Furthermore, it is no more necessary to set wide spacing between wirings. Still furthermore, the occurrence of noise is prevented.

Abstract: A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated S101, a clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated S102. When the allocated resource connection graph includes nodes to which hardware resources having the same function are allocated, a sharing edge for controlling sharing of the nodes is added between the nodes S103. A provisional layout of the allocated resource connection graph having the sharing edge added thereto is provided S104, and the nodes of the allocated resource connection graph are shared based on the layout result S105. The sharing edge is provided with attribute or weight such as attraction or repulsion. Thus, the distance between the nodes in the layout result is controlled and the degree at which the resources are shared is controlled.

Abstract: In design of particularly large-scale, complicated semiconductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj+Wmax+T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj−Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.

Abstract: In design of particularly large-scale, complicated semiconductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj+Wmax+T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj−Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.

Abstract: A method for designing a layout of a semiconductor device includes the steps of: a) preparing a first layout corresponding to a first netlist and including a component layout and a number n of, or first to nth (where n≧2), interconnection planar layouts to be sequentially stacked on the component layout; b) receiving a second netlist, which is different from the first netlist; c) selecting at least one of the interconnection planar layouts from the first layout, the number of the interconnection planar layouts selected being equal to or smaller than n−1; and d) producing a second layout, corresponding to the second netlist, by changing the physical arrangement of the at least one interconnection planar layout selected, the second layout including the component layout, the at least one interconnection planar layout with the changed arrangement, and the other interconnection planar layouts that have not been selected from the first layout.

Abstract: An initial arrangement is effected based on a net list and a cell library. Combination functions are extracted from a cost function. An optimum estimated temperature is calculated based on the difference between values of the cost function before and after two adjacent elements that have been selected randomly from elements to be arranged are interchanged in position, while near-optimum estimated temperatures are calculated based on the differences between respective values of the combination functions before and after the positional interchange. Of the near-optimum estimated temperatures, those lower than the optimum estimated temperature are recorded in a temperature schedule list together with the optimum estimated temperature. Thereafter, the Monte-Carlo method based on a random positional interchange between the elements to be arranged using the cost function is executed in order of the decreasing temperatures recorded in the temperature schedule list, whereby the initial arrangement is improved.

Abstract: In design of particularly large-scale, complicated semi-conductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj+Wmax+T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj−Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.

Abstract: Based on a relative comparison of respective consumed powers of cells which are subjected to a layout, separation information on cells to be separated which are to be arranged in a spaced-apart manner from each other is generated by separation information generating means, and a layout is generated by layout generating means based on this separation information. Accordingly, it is no more necessary to rearrange cells or to form a layout of the entire circuit again after generating an initial layout. Furthermore, it is no more necessary to set wide spacing between wirings. Still furthermore, the occurrence of noise is prevented.

Abstract: Based on the arrangement of a plurality of synchronous devices in an integrated circuit or on timing constraints, a group of discrete clock delay values composed of a finite number of discrete values to be allocated as respective clock delay values to the individual synchronous devices is determined. Then, the clock delay value selected from the group of discrete clock delay values is allocated as a selected clock delay value to each of the synchronous devices, while the operation of the integrated circuit is ensured. Thereafter, a clock circuit for supplying a clock signal to each of the synchronous devices in accordance with the selected clock delay value is designed.

Abstract: Based on a relative comparison of respective consumed powers of cells which are subjected to a layout, separation information on cells to be separated which are to be arranged in a spaced-apart manner from each other is generated by separation information generating means, and a layout is generated by layout generating means based on this separation information. Accordingly, it is no more necessary to rearrange cells or to form a layout of the entire circuit again after generating an initial layout. Furthermore, it is no more necessary to set wide spacing between wirings. Still furthermore, the occurrence of noise is prevented.

Abstract: In a semiconductor integrated circuit, a CMOS logic circuit receives a voltage from a power-source line, while releasing a current through a ground line. A constant-voltage auxiliary circuit is disposed in parallel with the CMOS logic circuit. The constant-voltage auxiliary circuit receives an output signal from the CMOS logic circuit. The constant-voltage auxiliary circuit consumes power when the output signal from the CMOS logic circuit is stable to maintain a potential difference between the power-source line and the ground line at a specified voltage and halts power consumption when the output signal from the CMOS logic circuit is inverted, i.e., when the potential difference is decreasing, thereby suppressing the decrease of the potential difference. Accordingly, voltage fluctuations on the power-source line are suppressed.

Abstract: In design of particularly large-scale, complicated semiconductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj+Wmax+T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj−Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.

Abstract: A semiconductor integrated circuit includes: a first register connected to the input of a first group of logic devices; a second register connected between the first and second groups of logic devices; and a third register connected to the output of the second group of logic devices. The integrated circuit is designed in the following manner. First, a shortest one of delays caused by respective signal propagation paths between the first and second registers and a shortest one of delays caused by respective signal propagation paths between the second and third registers are added together to obtain a shortest total delay. Next, if the shortest total delay is longer than a time obtained by subtracting one clock cycle time from a sum of constraint times defining respective signal propagation times between the first and second registers and between the second and third registers, then the second register is removed, thereby connecting the first and second groups of logic devices together.

Abstract: An initial placement is performed based on a net list and a cell library. An optimum effective temperature Tc is derived based on a cost value obtained if the positions of two components, selected from a list of exchange candidates (where all the components are registered), are exchanged with each other and a cost value before the exchange is performed. A first component and a second component, adjacent to the first component, are selected from the list of exchange candidates and the positions thereof are exchanged with each other. And at the optimum effective temperature Tc, it is determined in accordance with a Monte-Carlo method using the cost values before and after the exchange whether or not the exchange is allowable. If it is allowable, the placement after the exchange is decided as a new placement. Otherwise, the placement before the exchange is decided as a new placement.

Abstract: Logic circuits are experimentally automatically synthesized, and a representative line length of each fanout number is estimated on the basis of a net list resulting from the synthesis. The representative line length corresponds to a length of a line positioned at a center when plural lines are aligned in the order of their lengths (namely, a median line length WLmed(fn)). Furthermore, a standard deviation .sigma.med(fn) and a probability coefficient K(fn) of the deviation are calculated with regard to each fanout number on the basis of the net list. Then, a defined line length WL(fn) of each fanout number fn is calculated by using an expression, WL(fn) =WLmed(fn)+K(fn).multidot..sigma.med(fn). At this point, when there is a demand for design of an LSI having a high operation speed, the probability coefficient K(fn) is set at a small value, and when there is a demand for design of an LSI completed in a short period of time, the probability coefficient K(fn) is set at a large value.

Abstract: In a semiconductor integrated circuit, a CMOS logic circuit receives a voltage from a power-source line, while releasing a current through a ground line. A constant-voltage auxiliary circuit is disposed in parallel with the CMOS logic circuit. The constant-voltage auxiliary circuit receives an output signal from the CMOS logic circuit. The constant-voltage auxiliary circuit consumes power when the output signal from the CMOS logic circuit is stable to maintain a potential difference between the power-source line and the ground line at a specified voltage and halts power consumption when the output signal from the CMOS logic circuit is inverted, i.e., when the potential difference is decreasing, thereby suppressing the decrease of the potential difference. Accordingly, voltage fluctuations on the power-source line are suppressed.

Abstract: An LSI layout design technique is disclosed which has the ability to satisfy LSI timing constraints in a short processing time. A netlist descriptive of a target circuit that is designed is fed to a computer, and a flip-flop netlist representing information about connections among flip-flops relating to the timing constraints, is generated from the netlist. Such a flip-flop netlist is generated by clustering using a flip-flop as a seed. According to the generated flip-flop netlist, each flip-flop is placed and a flip-flop region to place therein a cell relating to a flip-flop is determined. A cell relating to a corresponding flip-flop is placed in a flip-flop region and the cell arrangement is improved throughout the placement region. Based on the improved cell arrangement, a layout is designed.

Abstract: The wire length of an LSI is estimated from a netlist describing connection information of the LSI and a cell library storing information as to cells used in the LSI design, with performing no rough placement and rough wiring by a layout system. Information necessary for wire length estimation is extracted from the netlist and the cell library. A net basic wire length is determined for each fan-out. In a net wire length estimating step, a net wire length for each fan-out is estimated by making reference to the determined net basic wire length and taking into account net expansion due to the cell distribution in a cell placement. Additionally, taking into account a terminal distribution and the aspect ratio of an estimation-target block, a correction on the estimated net wire length is made. From the corrected net wire length, the total wire length of the estimation-target block is estimated.

Abstract: A netlist between functional macros is entered. Based on the netlist, an outline layout process for a functional macro is performed and physical specifications for the functional macro are determined from an outline layout produced by the outline layout process. Thereafter, a logic synthesis process is performed on the basis of the physical specifications determined. Based on the outline layout, a logic, obtained by the logic synthesis, is laid out. This makes it possible to reduce the number of times a circuit synthesis process is redone, taking into account a laying-out at an upper-stage functional design process in which no gate level is specified. For this reason, an improved LSI automatic design method is provided which is able to complete an LSI layout design, in which the LSI area and the LSI delay value are optimized, in a short period of time.