Abstract: A shared memory system provides an access monitoring mechanism 112 with a definition for taking clusters for motion picture attributes as pieces of cluster memory 1 and 2. When a DSP (2) 104 makes access to memory while adding attribute information about an image to the access, the access monitoring mechanism 112 outputs to a cluster memory space selector 119 control information 131 that permits making of access to the pieces of cluster memory 1 and 2. Based on the control information 131, the cluster memory space selector 119 sorts access from the DSP (2) 104 to the cluster memory 1 or 2. The same also applies to access from a GPU 105. A plurality of master processors share shared memory 110 divided into a plurality of clusters 111, thereby holding coherence of cache memory.

Abstract: An asymmetric multiprocessor capable of increasing a degree of freedom of distributed processing, minimizing a processing load on each processor (CPU), and achieving a large reduction in power consumption by reducing an operating frequency or lowering the power supply voltage. An asymmetric multiprocessor includes a hardware resource mediator that mediates request signals requesting permission to use arbitrary hardware accelerators from CPU cores. A signal processing content selector selects signal processing content of a dynamically reconfigurable signal processor that is connected as a slave A clock skew mediator arbitrarily shifts a clock phase relationship among groups, while clock delay generators delay a clock signal based on a clock skew selection enable signal.

Abstract: An asymmetric multiprocessor capable of increasing the degree of freedom of distributed processing, minimizing the processing load on each processor (CPU), and achieving a large reduction in power consumption by reducing the operating frequency or lowering the power supply voltage. Asymmetric multiprocessor (100) includes a hardware resource mediation section (110) that mediates request signals requesting permission to use arbitrary hardware accelerators from CPU cores (101a and 101b) ; a signal processing content selection section (111) that selects signal processing content of dynamically reconfigurable signal processor section (107) connected as a slave; a clock skew mediation section (112) that performs control to arbitrarily shift a clock phase relationship among groups; and clock delay generation sections (113a through 113g) that delay a clock signal based on clock skew selection enable signal (114).

Abstract: In scan test circuit design, a plurality of flipflop circuits (102a, 102b or 102c) driven with each of final-stage elements 101f of a clock tree T are connected in series, to form a sub-scan chain. Also, sub-scan chains smallest in the relative difference in the number of stages of delay elements existing from the clock supply point S of the clock tree T (i.e., sub-scan chains different by one stage) are connected to each other. Further, sub-scan chains are connected so that data shift be made from a flipflop circuit larger in clock delay to a flipflop circuit smaller in clock delay. This reduces the number of delay elements inserted in data lines of a shift register for hold time guarantee in shift operation of the scan shift register, and suppresses power consumption.