Patents by Inventor Masahiro Inohara
Masahiro Inohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10957641Abstract: According to one embodiment, a semiconductor device includes a substrate, a first conductive layer, a second conductive layer, and a contact plug. The first conductive layer is disposed on the substrate and contains a metal silicide. The second conductive layer is disposed on the first conductive layer and contains a metal having bond dissociation energy larger than bond dissociation energy of the metal silicide. The contact plug is disposed on the second conductive layer and includes a main body portion, and a peripheral portion disposed on the surface of the main body portion and containing titanium.Type: GrantFiled: February 27, 2020Date of Patent: March 23, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Masahiro Inohara
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Publication number: 20200194369Abstract: According to one embodiment, a semiconductor device includes a substrate, a first conductive layer, a second conductive layer, and a contact plug. The first conductive layer is disposed on the substrate and contains a metal silicide. The second conductive layer is disposed on the first conductive layer and contains a metal having bond dissociation energy larger than bond dissociation energy of the metal silicide. The contact plug is disposed on the second conductive layer and includes a main body portion, and a peripheral portion disposed on the surface of the main body portion and containing titanium.Type: ApplicationFiled: February 27, 2020Publication date: June 18, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Masahiro INOHARA
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Patent number: 10615115Abstract: According to one embodiment, a semiconductor device includes a substrate, a first conductive layer, a second conductive layer, and a contact plug. The first conductive layer is disposed on the substrate and contains a metal silicide. The second conductive layer is disposed on the first conductive layer and contains a metal having bond dissociation energy larger than bond dissociation energy of the metal silicide. The contact plug is disposed on the second conductive layer and includes a main body portion, and a peripheral portion disposed on the surface of the main body portion and containing titanium.Type: GrantFiled: March 1, 2018Date of Patent: April 7, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventor: Masahiro Inohara
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Publication number: 20190088592Abstract: According to one embodiment, a semiconductor device includes a substrate, a first conductive layer, a second conductive layer, and a contact plug. The first conductive layer is disposed on the substrate and contains a metal silicide. The second conductive layer is disposed on the first conductive layer and contains a metal having bond dissociation energy larger than bond dissociation energy of the metal silicide. The contact plug is disposed on the second conductive layer and includes a main body portion, and a peripheral portion disposed on the surface of the main body portion and containing titanium.Type: ApplicationFiled: March 1, 2018Publication date: March 21, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Masahiro INOHARA
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Patent number: 9576948Abstract: A semiconductor device includes a first and second transistor. Each of the first and the second transistors includes a well of a first conductivity type, a band-shaped region provided on the well, a drain region of a second conductivity type provided on the well, and a gate electrode. The band-shaped region, the drain region and the gate electrode extend in a first direction. The band-shaped region includes a back gate region of the first conductivity type and a source region of the second conductivity type. The back gate region and the source region are arranged alternately along the first direction in the band-shaped region. A ratio of a length of the source region to a length of the back gate region along the first direction of the first transistor is greater than the ratio of the second transistor.Type: GrantFiled: June 23, 2015Date of Patent: February 21, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Kanako Komatsu, Keita Takahashi, Masahiro Inohara
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Patent number: 9318548Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first electrode, and a first insulating film. The semiconductor layer is provided on the semiconductor substrate. The semiconductor layer includes first-fifth regions. The first region includes a first portion and a second portion arranged with the first portion. The second region is provided in a surface of the first portion. The third region is provided between the second portion and the second region in the surface of the first portion. The fourth region is provided between the second portion and the third region in the surface of the first portion. The fifth region is provided in a surface of the fourth region. The first electrode is provided between the fifth region and the second portion on the semiconductor layer. The first insulating film is provided between the semiconductor layer and the first electrode.Type: GrantFiled: March 10, 2015Date of Patent: April 19, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Yasunori Iwatsu, Masahiro Inohara
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Publication number: 20160079348Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first electrode, and a first insulating film. The semiconductor layer is provided on the semiconductor substrate. The semiconductor layer includes first-fifth regions. The first region includes a first portion and a second portion arranged with the first portion. The second region is provided in a surface of the first portion. The third region is provided between the second portion and the second region in the surface of the first portion. The fourth region is provided between the second portion and the third region in the surface of the first portion. The fifth region is provided in a surface of the fourth region. The first electrode is provided between the fifth region and the second portion on the semiconductor layer. The first insulating film is provided between the semiconductor layer and the first electrode.Type: ApplicationFiled: March 10, 2015Publication date: March 17, 2016Inventors: Yasunori Iwatsu, Masahiro Inohara
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Publication number: 20150380546Abstract: A semiconductor device includes a first and second transistor. Each of the first and the second transistors includes a well of a first conductivity type, a band-shaped region provided on the well, a drain region of a second conductivity type provided on the well, and a gate electrode. The band-shaped region, the drain region and the gate electrode extend in a first direction. The band-shaped region includes a back gate region of the first conductivity type and a source region of the second conductivity type. The back gate region and the source region are arranged alternately along the first direction in the band-shaped region. A ratio of a length of the source region to a length of the back gate region along the first direction of the first transistor is greater than the ratio of the second transistor.Type: ApplicationFiled: June 23, 2015Publication date: December 31, 2015Inventors: Kanako Komatsu, Keita Takahashi, Masahiro Inohara
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Publication number: 20150263090Abstract: According to one embodiment, a semiconductor device includes a silicon substrate, a first semiconductor element, a first semiconductor layer, and a second semiconductor element. The silicon substrate includes a first portion and a second portion. The first portion has a first face. The second portion has a second face. An angle between the first face and the second face is 125 degrees or more and 126 degrees or less. The first semiconductor element is provided at the first portion. The first semiconductor layer is provided on the second face. The second semiconductor element is provided at the first semiconductor layer.Type: ApplicationFiled: September 8, 2014Publication date: September 17, 2015Inventor: Masahiro INOHARA
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Patent number: 8970048Abstract: A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects.Type: GrantFiled: December 30, 2011Date of Patent: March 3, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Masahiro Inohara
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Patent number: 8629437Abstract: According to embodiments, there is provided a semiconductor device, including: a logic circuit; an interlayer insulating film formed above the logic circuit; an amorphous silicon layer including: a non-silicide layer formed on the interlayer insulating film; and a silicide layer formed on the non-silicide layer; a TFT formed on the amorphous silicon layer; and a contact plug formed to plug a through hole penetrating the interlayer insulating film, the contact plug being electrically connected to the logic circuit, an upper part of the contact plug being connected to the silicide layer.Type: GrantFiled: March 18, 2011Date of Patent: January 14, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuya Ishida, Masahiro Inohara
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Patent number: 8546518Abstract: A method is provided for producing a polyarylene sulfide by reacting a sulfidizing agent with a dihalogenated aromatic compound in an organic polar solvent in the presence of an alkali metal hydroxide, the method includes <Step 1>: carrying out the reaction in such a manner that the polymerization time in a temperature range of 230° C. to less than 245° C. (T1a) is not less than 30 minutes and less than 3.5 hours and that the conversion ratio of the dihalogenated aromatic compound at the end of the step is 70 to 98 mol. % and <Step 2>: carrying out the reaction in such a manner that the polymerization time in a temperature range of 245° C. to less than 280° C. (T2) is not less than 5 minutes and less than 1 hour.Type: GrantFiled: August 26, 2010Date of Patent: October 1, 2013Assignee: Toray Industries, Inc.Inventors: Takeshi Unohara, Hiroyuki Isago, Toru Nishimura, Masahiro Inohara
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Patent number: 8252692Abstract: A semiconductor device according to one embodiment includes: a substrate having an element region where a semiconductor element is formed; a via hole formed in a portion of the substrate adjacent to the element region; a conducting portion provided in the via hole via an insulating layer; and a buffer layer provided between the substrate and the insulating layer, wherein the buffer layer is made of a material in which a difference in thermal expansion coefficient between the substrate and the buffer layer is smaller than that between the substrate and the insulating layer.Type: GrantFiled: June 27, 2011Date of Patent: August 28, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Masahiro Inohara
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Publication number: 20120178898Abstract: A method is provided for producing a polyarylene sulfide by reacting a sulfidizing agent with a dihalogenated aromatic compound in an organic polar solvent in the presence of an alkali metal hydroxide, the method includes <Step 1>: carrying out the reaction in such a manner that the polymerization time in a temperature range of 230° C. to less than 245° C. (T1a) is not less than 30 minutes and less than 3.5 hours and that the conversion ratio of the dihalogenated aromatic compound at the end of the step is 70 to 98 mol. % and <Step 2>: carrying out the reaction in such a manner that the polymerization time in a temperature range of 245° C. to less than 280° C. (T2) is not less than 5 minutes and less than 1 hour.Type: ApplicationFiled: August 26, 2010Publication date: July 12, 2012Applicant: Toray Industries, Inc.Inventors: Takeshi Unohara, Hiroyuki Isago, Toru Nishimura, Masahiro Inohara
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Publication number: 20120104576Abstract: A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects.Type: ApplicationFiled: December 30, 2011Publication date: May 3, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Masahiro INOHARA
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Publication number: 20120068179Abstract: According to embodiments, there is provided a semiconductor device, including: a logic circuit; an interlayer insulating film formed above the logic circuit; an amorphous silicon layer including: a non-silicide layer formed on the interlayer insulating film; and a silicide layer formed on the non-silicide layer; a TFT formed on the amorphous silicon layer; and a contact plug formed to plug a through hole penetrating the interlayer insulating film, the contact plug being electrically connected to the logic circuit, an upper part of the contact plug being connected to the silicide layer.Type: ApplicationFiled: March 18, 2011Publication date: March 22, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuya Ishida, Masahiro Inohara
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Patent number: 8102059Abstract: A higher aspect ratio for upper level metal interconnects is described for use in higher frequency circuits. Because the skin effect reduces the effective cross-sectional area of conductors at higher frequencies, various approaches are described to reduce the effective RC delay in interconnects.Type: GrantFiled: March 11, 2009Date of Patent: January 24, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Masahiro Inohara
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Publication number: 20110256703Abstract: A semiconductor device according to one embodiment includes: a substrate having an element region where a semiconductor element is formed; a via hole formed in a portion of the substrate adjacent to the element region; a conducting portion provided in the via hole via an insulating layer; and a buffer layer provided between the substrate and the insulating layer, wherein the buffer layer is made of a material in which a difference in thermal expansion coefficient between the substrate and the buffer layer is smaller than that between the substrate and the insulating layer.Type: ApplicationFiled: June 27, 2011Publication date: October 20, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Masahiro Inohara
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Patent number: 7994641Abstract: A semiconductor device according to one embodiment includes: a substrate having an element region where a semiconductor element is formed; a via hole formed in a portion of the substrate adjacent to the element region; a conducting portion provided in the via hole via an insulating layer; and a buffer layer provided between the substrate and the insulating layer, wherein the buffer layer is made of a material in which a difference in thermal expansion coefficient between the substrate and the buffer layer is smaller than that between the substrate and the insulating layer.Type: GrantFiled: June 26, 2009Date of Patent: August 9, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Masahiro Inohara
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Publication number: 20100317615Abstract: A method of enhancing ocular penetration of a drug in an eyedrop by administering to an eye, an eyedrop containing, particulate agar having a weight-average molecular weight of from 5,000 to 1,200,000, the particulate agar being obtained by dissolving agar into an aqueous solution by heating and then cooling the resultant mixture to avoid gelling, while applying a stress by vibration, shearing, stirring, compression or pulverizing, wherein the particulate agar is in an amount of 0.1 to 10 wt %.Type: ApplicationFiled: August 16, 2010Publication date: December 16, 2010Applicants: TORAY INDUSTRIES, INC., SANTEN PHARMACEUTICAL CO., LTD.Inventors: Masahiro Inohara, Masahito Yoshikawa, Takashi Taniguchi, Mitsuru Yokota, Naoki Shimoyama, Masaki Ue, Miho Araki