Patents by Inventor Masahiro Kiyooka

Masahiro Kiyooka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096423
    Abstract: A memory system includes a semiconductor memory that includes a cell unit having a plurality of memory cells, and a control circuit for controlling the plurality of memory cells, and a memory controller configured to control the semiconductor memory. The control circuit is configured to execute a data read operation on the cell unit by using one or more read voltages, acquire first data by the data read operation, generate second data with a data size smaller than the first data, based on the first data, and transmit the second data to the memory controller. The memory controller is configured to determine, based on the second data, whether or not to rewrite the page data written in the cell unit.
    Type: Application
    Filed: March 2, 2023
    Publication date: March 21, 2024
    Inventors: Dongxiao YU, Masahiro KIYOOKA, Suguru NISHIKAWA, Yoshihisa KOJIMA
  • Patent number: 11909415
    Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: February 20, 2024
    Assignee: Kioxia Corporation
    Inventors: Masahiro Kiyooka, Riki Suzuki, Yoshihisa Kojima
  • Patent number: 11768732
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: September 26, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Yuta Kumano, Hironori Uchikawa, Kosuke Morinaga, Naoaki Kokubun, Masahiro Kiyooka, Yoshiki Notani, Kenji Sakurada, Daiki Watanabe
  • Publication number: 20230096401
    Abstract: A memory system according to an embodiment includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of memory cells. The memory controller is configured to control the nonvolatile memory. In read operation for the memory cells, the memory controller is configured to: perform tracking including a plurality of reads in which a read voltage is shifted; determine a hard bit read voltage based on results of the tracking; calculate a soft bit read voltage based on the determined hard bit read voltage; perform soft bit read using the calculated soft bit read voltage; and perform a soft bit decoding process using a result of the soft bit read and a log-likelihood ratio table associated with the calculated soft bit read voltage.
    Type: Application
    Filed: March 14, 2022
    Publication date: March 30, 2023
    Applicant: Kioxia Corporation
    Inventors: Masahiro KIYOOKA, Riki SUZUKI, Yoshihisa KOJIMA
  • Publication number: 20220075686
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta KUMANO, Hironori UCHIKAWA, Kosuke MORINAGA, Naoaki KOKUBUN, Masahiro KIYOOKA, Yoshiki NOTANI, Kenji SAKURADA, Daiki WATANABE
  • Patent number: 11210163
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: December 28, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuta Kumano, Hironori Uchikawa, Kosuke Morinaga, Naoaki Kokubun, Masahiro Kiyooka, Yoshiki Notani, Kenji Sakurada, Daiki Watanabe
  • Patent number: 10803930
    Abstract: According to one embodiment, a memory system comprising includes a semiconductor memory and a memory controller. The memory controller is configured to obtain first data read from the semiconductor memory using a first voltage, obtain second data read from the semiconductor memory using a second voltage, calculate a first value for a first section of the first data using the first data and the second data, calculate a second value for a second section of the first data using the first data and the second data, calculate a third value for a third section of the first data using the first data and the second data, and correct an error of the first data using the first to third values.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masahiro Kiyooka, Yoshihisa Kojima, Toshikatsu Hida
  • Publication number: 20200081770
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yuta Kumano, Hironori Uchikawa, Kosuke Morinaga, Naoaki Kokubun, Masahiro Kiyooka, Yoshiki Notani, Kenji Sakurada, Daiki Watanabe
  • Publication number: 20190295635
    Abstract: According to one embodiment, a memory system comprising includes a semiconductor memory and a memory controller. The memory controller is configured to obtain first data read from the semiconductor memory using a first voltage, obtain second data read from the semiconductor memory using a second voltage, calculate a first value for a first section of the first data using the first data and the second data, calculate a second value for a second section of the first data using the first data and the second data, calculate a third value for a third section of the first data using the first data and the second data, and correct an error of the first data using the first to third values.
    Type: Application
    Filed: September 6, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Masahiro KIYOOKA, Yoshihisa KOJIMA, Toshikatsu HIDA
  • Publication number: 20190220348
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value read from the non-volatile memory to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.
    Type: Application
    Filed: September 11, 2018
    Publication date: July 18, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Naoaki KOKUBUN, Masahiro KIYOOKA, Yoshiki NOTANI, Kenji SAKURADA, Daiki WATANABE, Hironori UCHIKAWA
  • Patent number: 9984731
    Abstract: According to one embodiment, a storage device includes a plurality of nonvolatile semiconductor memories, a sensor and a controller. The sensor is configured to measure a temperature of the nonvolatile semiconductor memories. The controller is configured to receive data from a host, determine a rewriting interval of the data and write the data to, of the nonvolatile semiconductor memories, a nonvolatile semiconductor memory having a temperature corresponding to the rewriting interval.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: May 29, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Masahiro Kiyooka
  • Publication number: 20170068466
    Abstract: According to one embodiment, a storage device includes a plurality of nonvolatile semiconductor memories, a sensor and a controller. The sensor is configured to measure a temperature of the nonvolatile semiconductor memories. The controller is configured to receive data from a host, determine a rewriting interval of the data and write the data to, of the nonvolatile semiconductor memories, a nonvolatile semiconductor memory having a temperature corresponding to the rewriting interval.
    Type: Application
    Filed: December 16, 2015
    Publication date: March 9, 2017
    Inventor: Masahiro Kiyooka