Abstract: Disclosed is a composition for use in controlling ectoparasites, comprising as an active ingredient at least one of compounds represented by formula (I) or (III) or salts thereof. The present invention provides a composition for use in controlling ectoparasites that has excellent ectoparasite control effect and is highly safe.

Abstract: Disclosed is a composition for use in controlling harmful organisms, comprising as active ingredients at least one of 16-keto aspergillimide, its enantiomers, their mixture, or their acid addition salts and at least one of other harmful organism control agents. The present invention provides a composition for use in controlling harmful organisms that has excellent insecticidal activity or penetrative transferable insecticidal activity against a wide range of harmful organisms, particularly agricultural and horticultural insect pests.

Abstract: When an operation of a specified one of monitor circuits is defective or any of elements forming a ring oscillator in each of the monitor circuits has characteristic abnormality, if voltage control is performed based on a result from the monitor operating at a lowest speed, a required voltage may be overestimated. This results in an increase in power consumption, and also causes an accuracy reduction when the average value of detection results from the multiple monitors is calculated. The multiple monitor circuits are provided. Of the detection results therefrom, any detection result falling outside a predetermined range is ignored, and the average value of the remaining monitor results is used as a final monitor detection value.

Abstract: A substrate bias is controlled such that a leakage current is minimum. A semiconductor integrated circuit device comprises a leakage detecting circuit which detects a leakage current by using leakage detecting MOSFETs, a control circuit which generates a control signal depending on an output from the leakage detecting circuit, a substrate bias generating circuit which changes a substrate bias depending on the control signal, and a controlled circuit including a MOSFET having the same characteristics as that of each of the leakage detecting MOSFETs. The leakage detecting circuit detects a substrate leakage current which includes as the substrate bias becomes deep and a subthreshold leakage current which decreases as the substrate bias becomes deep.

Abstract: A semiconductor integrated circuit device includes: a target circuit whose at least power supply voltage is variable; a power supply voltage providing circuit feeding the target circuit with a power supply voltage; and a minimum energy point monitor circuit detecting an energy-minimizing power supply voltage which minimizes a change in the energy consumed by the target circuit upon a change in the power supply voltage. The power supply voltage delivered by the power supply voltage providing circuit is controlled so as to be equal to the energy-minimizing power supply voltage detected by the minimum energy point monitor circuit.

Abstract: A control circuit controls a power-source-voltage feed circuit, and controls a power source voltage fed to a target circuit. A reference-speed monitor monitors whether or not a delay time of a critical path in the target circuit is satisfies a required operational speed. A voltage-difference monitor monitors a difference between the power source voltage of the target circuit and a threshold voltage of the target circuit, to output the voltage difference information. The control circuit determines whether to increase or decrease the power source voltage based on a result of monitoring by the reference-speed monitor. The control circuit determines the change rate of the power source voltage so that the control rate of the power source voltage is proportional to the voltage difference information output from the voltage-difference monitor.

Abstract: A semiconductor integrated circuit is capable of accurately detecting the characteristics of a chip. The semiconductor integrated circuit includes a monitor circuit and a control circuit. The control circuit generates a clock pulse signal having M successive pulses (M is 2 or a greater integer), and outputs the clock pulse signal to the monitor circuit. The monitor circuit includes a frequency divider and a ring oscillator. The frequency divider frequency divides the clock pulse signal by M and generates the resulting signal as an enable signal. The ring oscillator generates an oscillation signal as a monitor output value during a period defined in accordance with the enable signal.

Abstract: A semiconductor integrated circuit includes a first circuit part that is designed under a first corner condition with respect to a process variation, a second circuit part that is designed under a second corner condition narrower than the first condition, and a control part that changes an operating voltage supplied to the first circuit part and the second circuit part according to a delay amount of the first circuit part, and starts the second circuit part when a delay characteristic caused by a change in the operating voltage conforms to a delay characteristic under the second corner condition.

Abstract: There is provided a high-strength hot rolled steel sheet excellent in phosphatability, wherein a maximum depth (Ry) of pits and bumps, existing on a surface thereof, is not less than 10 ?m, and an average interval (Sm) of the pits and the bumps is not more than 30 ?m, meeting either a requirement for a load length ratio (tp40) of the pits and the bumps on the surface at not more than 20%, or a requirement for a difference between a load length ratio (tp60) and the load length ratio (tp40), at not less than 60%, or both thereof. The high-strength hot rolled steel sheet is capable of exhibiting stable and excellent phosphatability even if Mo highly effective for reinforcement in strength is added thereto in expectation of a higher strength.

Abstract: The present invention relates to cyclic amino benzoic acid derivatives which are effective in therapy of lipid metabolism abnormality, diabetes and the like as a human peroxisome proliferators-activated receptor (PPAR) agonist, in particular, as an agonist against human PPAR? isoform, and addition salts thereof, and pharmaceutical compositions containing these compounds. A cyclic amino benzoic acid derivative represented by the general formula (1) [wherein a ring Ar represents an aryl group which may have substituent, or the like; Y represents a C1-C4 alkylene, C2-C4 alkenylene, C2-C4 alkynylene, or the like; Z represents an oxygen atom, sulfur atom or —(CH2)n— (n represents 0, 1 or 2); X represents a hydrogen atom, halogen atom, lower alkyl group which may be substituted with a halogen atom, or the like; R represents a hydrogen atom or lower alkyl group, and —COOR substitutes for an ortho position or metha position of binding position of ring W] or a pharmaceutically acceptable salt thereof.

Abstract: Provided herein are spirocyclic aminoquinolones of formula I and compositions containing the compounds. The compounds and compositions provided herein are useful in the prevention, amelioration or treatment of GSK-3 inhibitors mediated diseases. In Formula (I): X1 is O or NR8; A is bond or substituted or unsubstituted C1-C2 alkylene, wherein the substituents when present are selected from one to four Q2 groups; where Q2 is alkyl or haloalkyl; p is 0 or 1; and q is an integer of 0 to 2.

Abstract: A semiconductor integrated circuit device includes: a target circuit whose at least power supply voltage is variable; a power supply voltage providing circuit feeding the target circuit with a power supply voltage; and a minimum energy point monitor circuit detecting an energy-minimizing power supply voltage which minimizes a change in the energy consumed by the target circuit upon a change in the power supply voltage. The power supply voltage delivered by the power supply voltage providing circuit is controlled so as to be equal to the energy-minimizing power supply voltage detected by the minimum energy point monitor circuit.

Abstract: A power supply voltage control circuit controls power supply voltage supplied to a target circuit that performs certain signal processing. The power supply voltage control circuit includes a control signal generation circuit that selectively generates first and second control signals when the power supply voltage supplied to the target circuit is increased from a first power supply voltage to a second power supply voltage, the second power supply voltage being higher than the first power supply voltage, and a power supply circuit that increases the power supply voltage toward a voltage level of the second power supply voltage based on the first control signal, or increases the power supply voltage to a voltage level higher than the second power supply voltage first and subsequently decreases the power supply voltage to the second power supply voltage based on the second control signal.

Abstract: A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

Abstract: Provided herein are aminoquinolones of formula I and compositions containing the compounds. The compounds and compositions provided herein are useful in the prevention, amelioration or treatment of GSK-3 inhibitors mediated diseases.

Abstract: The present invention relates to a semiconductor device including a Fin type field effect transistor (FET) having a protrusive semiconductor layer protruding from a substrate plane, a gate electrode formed so as to straddle the protrusive semiconductor layer, a gate insulating film between the gate electrode and the protrusive semiconductor layer, and source and drain regions provided in the protrusive semiconductor layer, wherein the semiconductor device has on a semiconductor substrate an element forming region having a Fin type FET, a trench provided on the semiconductor substrate for separating the element forming region from another element forming region, and an element isolation insulating film in the trench; the element forming region has a shallow substrate flat surface formed by digging to a depth shallower than the bottom surface of the trench and deeper than the upper surface of the semiconductor substrate, a semiconductor raised portion protruding from the substrate flat surface and formed of a p

Abstract: A plurality of delay paths are connected in parallel between two synchronous operation circuits operating in synchronism with a clock signal CLK, and enable transmission of a signal. A delay detection unit detects the respective delay times of the plurality of delay paths, and a control unit selects one delay path from among the plurality of delay paths based on the detection results from the delay detection unit, and controls the blocking of signal transmission in the delay paths other than the selected one delay path.

Abstract: A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

Abstract: A level shifter in which short circuit current and the increase in delay are reduced when a first power source is controlled. In a level shifter for converting a signal level of a first logic circuit to which a first power source is supplied into a signal level of a second logic circuit to which a second power source is supplied, the circuit includes a switching circuit between a GND power source terminal of a level shift core circuit and a GND power source. The switching circuit is controlled by a third logic circuit which generates a control signal under control of the first power source, and a pull-up/pull-down circuit at an output of the level shift core circuit. The pull-up and/or pull-down circuit is controlled by the third logic circuit.

Abstract: A control circuit controls a power-source-voltage feed circuit, and controls a power source voltage fed to a target circuit. A reference-speed monitor monitors whether or not a delay time of a critical path in the target circuit is satisfies a required operational speed. A voltage-difference monitor monitors a difference between the power source voltage of the target circuit and a threshold voltage of the target circuit, to output the voltage difference information. The control circuit determines whether to increase or decrease the power source voltage based on a result of monitoring by the reference-speed monitor. The control circuit determines the change rate of the power source voltage so that the control rate of the power source voltage is proportional to the voltage difference information output from the voltage-difference monitor.