Patents by Inventor Masahiro Sekiguchi

Masahiro Sekiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240132099
    Abstract: A vehicle object detection system configured to generate a judgement on whether a target object which has been detected to enter the detection area is an alert object, and to output the judgement to a warning which is configured to warn a driver of the subject vehicle that a target object is present in the detection area behind the subject vehicle based on the judgement indicating that the target object is an alert object, wherein the system is configured to delay generating the judgement until a specified period of time has elapsed from a point in time when the target object entered the detection area from an adjacent area located lateral to the detection area and/or is configured to generate the judgement based on a change in distance between the target object and the subject vehicle during said specified period of time.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 25, 2024
    Applicants: Continental Autonomous Mobility Germany GmbH, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shoichi SEKIGUCHI, Takahiro KOHARA, Tomohiko MOCHIZUKI, Takayoshi NOHARA, Masahiro TAKAHASHI
  • Publication number: 20240078831
    Abstract: To determine the state of a subject person with a simple structure, an image determining device includes: an imaging unit that captures an image from a first direction, the image including the subject person; a first detector that detects size information from the image, the size information being about the subject person in the first direction; a second detector that detects position-related information, the position-related information being different from the information detected by the first detector; and a determining unit that determines the state of the subject person, based on a result of the detection performed by the first detector and a result of the detection performed by the second detector.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 7, 2024
    Applicant: NIKON CORPORATION
    Inventors: Tetsuya YAMAMOTO, Masahiro NEI, Isao TOTSUKA, Tomoyuki MATSUYAMA, Masamitsu YANAGIHARA, Satoshi HAGIWARA, Masakazu SEKIGUCHI
  • Publication number: 20160276532
    Abstract: According to one embodiment, semiconductor light emitting element includes: a substrate having a first surface and a second surface on an opposite side of the first surface; an insulating layer provided on the second surface of the substrate; a first metal layer provided on the insulating layer; a semiconductor light emitting unit provided on the first metal layer, the semiconductor light emitting unit including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer being electrically connected to the first metal layer; and a first electrode layer provided on the first surface of the substrate, the first electrode layer extending in the substrate and in the insulating layer, and the first electrode layer being electrically connected to the first metal layer.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 22, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kentaro MORI, Takeyuki Suzuki, Mie Matsuo, Masahiro Sekiguchi, Koji Kaga
  • Patent number: 8778778
    Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
  • Patent number: 8580652
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kawasaki, Kenichiro Hagiwara, Ikuko Inoue, Kazutaka Akiyama, Itsuko Sakai, Mie Matsuo, Masahiro Sekiguchi, Yoshiteru Koseki, Hiroki Neko, Koushi Tozuka, Kazuhiko Nakadate, Takuto Inoue
  • Patent number: 8338918
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Patent number: 8269315
    Abstract: A semiconductor device 1 has a through hole 3 formed in a second substrate 2. On the front surface of the semiconductor substrate 2, a first insulating layer 4 is coated having an opening 4a of the same diameter as that of the through hole 3, and a first wiring layer 5 is formed on the first insulating layer 4. Further, near the first wiring layer 5, the through hole 3 and a through connection portion constituted of a third insulating layer 8 formed on the inner surface and the like and a third wiring layer 9 filled and formed in the through hole 3 are formed. In addition, a second wiring layer 7 internally contacting the through connection portion is electrically connected with the first wiring layer 5. Between the inner surface of the through hole 3 and the first wiring layer 5, a second insulating layer 6 intervenes so that the first wiring layer 5 is separated from the third wiring layer 9 filled and formed in the through hole 3.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: September 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Kenji Takahashi
  • Patent number: 8237285
    Abstract: Semiconductor device includes semiconductor substrate, through hole having first opening and second opening, and including an expansion portion so that an opening area of first opening is greater than an opening area of lowermost portion of expansion portion, first insulating layer, and having an opening which communicates with through hole and has an area smaller than opening area of first opening, first wiring layer provided on first insulating layer, second insulating layer provided on expansion portion of through hole, and to cover first opening and an inner wall surface of through hole, second insulating layer having an opening communicating with opening of first insulating layer so as to expose first wiring layer through opening of first insulating layer, and second wiring layer provided on second insulating layer to extend from inside of through hole, and being connected to first wiring layer via openings of first and second insulating layers.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: August 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Mie Matsuo, Masahiro Sekiguchi, Chiaki Takubo
  • Patent number: 8228426
    Abstract: A semiconductor package includes a solid-state imaging element, electrode pad, through-hole electrode, and light-transmitting substrate. The solid-state imaging element is formed on the first main surface of a semiconductor substrate. The electrode pad is formed on the first main surface of the semiconductor substrate. The through-hole electrode is formed to extend through the semiconductor substrate between the first main surface and a second main surface opposite to the electrode pad formed on the first main surface. The light-transmitting substrate is placed on a patterned adhesive to form a hollow on the solid-state imaging element. The thickness of the semiconductor substrate below the hollow when viewed from the light-transmitting substrate is larger than that of the semiconductor substrate below the adhesive.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: July 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Atsuko Kawasaki, Kenji Takahashi, Masahiro Sekiguchi, Kazumasa Tanida
  • Publication number: 20120049312
    Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.
    Type: Application
    Filed: August 18, 2011
    Publication date: March 1, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa TANIDA, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
  • Patent number: 8063462
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface in which a light-receiving portion and electrodes are provided. The semiconductor substrate has a penetrating wiring layer connecting the first surface and the second surface. A light-transmissive protective member is disposed on the semiconductor substrate so as to cover the first surface. A gap is provided between the semiconductor substrate and the light-transmissive protective member. A protective film is formed at a surface of the light-transmissive protective member. The protective film has an opening provided at a region corresponding to the light-receiving portion.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Susumu Harada
  • Publication number: 20110241180
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 6, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Patent number: 7993974
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Publication number: 20110068476
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.
    Type: Application
    Filed: September 3, 2010
    Publication date: March 24, 2011
    Inventors: Atsuko KAWASAKI, Kenichiro Hagiwara, Ikuko Inoue, Kazutaka Akiyama, Itsuko Sakai, Mie Matsuo, Masahiro Sekiguchi, Yoshiteru Koseki, Hiroki Neko, Koushi Tozuka, Kazuhiko Nakadate, Takuto Inoue
  • Patent number: 7888760
    Abstract: A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major surface being on the opposite side of the first major surface; a circuit substrate provided with a circuit substrate electrode opposed to the second major surface; a connecting portion electrically connecting the backside interconnect electrode to the circuit substrate electrode; and a light shielding layer provided coplanar with the backside interconnect electrode or on the circuit substrate side of the backside interconnect electrode.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: February 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Sugiyama, Atsuko Yamashita, Kazutaka Akiyama, Susumu Harada, Masahiro Sekiguchi, Masayuki Dohi, Kazumasa Tanida, Chiaki Takubo, Hiroshi Yoshikawa, Akihiro Hori
  • Patent number: 7888778
    Abstract: A semiconductor device includes a semiconductor substrate having a through hole. An active layer is formed on a first surface of the semiconductor substrate. An inner wall surface of the through hole, a bottom surface of the through hole closed by the active layer and a second surface of the semiconductor substrate are covered with an insulating layer. A first opening is formed in the insulating layer which is present on the bottom surface of the through hole. A second opening is formed in the insulating layer which is present on the second surface of the semiconductor substrate. A first wiring layer is formed from within the through hole onto the second surface of the semiconductor substrate. A second wiring layer is formed to connect to the second surface through the second opening.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: February 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Ninao Sato, Kenji Takahashi
  • Patent number: 7808064
    Abstract: An imaging element is formed on the first main surface of a semiconductor substrate. An external terminal is formed on the second main surface of the semiconductor substrate. A through-hole electrode is formed in a through hole formed in the semiconductor substrate. A first electrode pad is formed on the through-hole electrode in the first main surface. An interlayer insulating film is formed on the first electrode pad and on the first main surface. A second electrode pad is formed on the interlayer insulating film. A passivation film is formed on the second electrode pad and the interlayer insulating film, and has an opening which exposes a portion of the second electrode pad. A contact plug is formed between the first and second electrode pads in a region which does not overlap the opening when viewed in a direction perpendicular to the surface of the semiconductor substrate.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: October 5, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kawasaki, Mie Matsuo, Ikuko Inoue, Masayuki Ayabe, Masahiro Sekiguchi, Kazumasa Tanida
  • Publication number: 20100025860
    Abstract: In one aspect of the present invention, a semiconductor device, may include a semiconductor substrate having a first surface and a second surface opposite to the first surface; a through hole in the semiconductor substrate, including an expansion portion which is provided in a vicinity of the first surface so that an opening area of the first opening is greater than an opening area of a lowermost portion of the expansion portion; a first insulating layer on the first surface of the semiconductor substrate; a first wiring layer on the first insulating layer to close the opening of the first insulating layer; a second insulating layer provided on the expansion portion of the through hole; and a second wiring layer on the second insulating layer to extend from inside of the through hole to the second surface of the semiconductor substrate.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 4, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa Tanida, Mie Matsuo, Masahiro Sekiguchi, Chiaki Takubo
  • Publication number: 20090284631
    Abstract: A semiconductor package includes a solid-state imaging element, electrode pad, through-hole electrode, and light-transmitting substrate. The solid-state imaging element is formed on the first main surface of a semiconductor substrate. The electrode pad is formed on the first main surface of the semiconductor substrate. The through-hole electrode is formed to extend through the semiconductor substrate between the first main surface and a second main surface opposite to the electrode pad formed on the first main surface. The light-transmitting substrate is placed on a patterned adhesive to form a hollow on the solid-state imaging element. The thickness of the semiconductor substrate below the hollow when viewed from the light-transmitting substrate is larger than that of the semiconductor substrate below the adhesive.
    Type: Application
    Filed: July 29, 2009
    Publication date: November 19, 2009
    Inventors: Mie MATSUO, Atsuko Kawasaki, Kenji Takahashi, Masahiro Sekiguchi, Kazumasa Tanida
  • Publication number: 20090283847
    Abstract: An imaging element is formed on the first main surface of a semiconductor substrate. An external terminal is formed on the second main surface of the semiconductor substrate. A through-hole electrode is formed in a through hole formed in the semiconductor substrate. A first electrode pad is formed on the through-hole electrode in the first main surface. An interlayer insulating film is formed on the first electrode pad and on the first main surface. A second electrode pad is formed on the interlayer insulating film. A passivation film is formed on the second electrode pad and the interlayer insulating film, and has an opening which exposes a portion of the second electrode pad. A contact plug is formed between the first and second electrode pads in a region which does not overlap the opening when viewed in a direction perpendicular to the surface of the semiconductor substrate.
    Type: Application
    Filed: July 23, 2009
    Publication date: November 19, 2009
    Inventors: Atsuko KAWASAKI, Mie Matsuo, Ikuko Inoue, Masayuki Ayabe, Masahiro Sekiguchi, Kazumasa Tanida