Abstract: A communication system that performs communication among a plurality of nodes by a broker-less type publishing/subscribing model, the communication system including a computer including a memory and a processor configured to receive communication data among the plurality of nodes; based on the communication data, create first relationship information indicating a relationship among the nodes regarding transmission and reception of the communication data, second relationship information indicating a relationship among the nodes regarding a belonging domain and whether the nodes are on a publisher side or on a subscriber side, and third relationship information indicating a relationship among the nodes regarding a topic to be published and subscribed; and create configuration information indicating a network configuration of the communication system by associating the first relationship information, the second relationship information, and the third relationship information.

Abstract: In a communication system that performs communication among a plurality of nodes by a broker-less type publishing/subscribing model, in a case where a network configuration of the communication system changes, an anomaly of the communication system is detected based on configuration information indicating the network configuration and at least one of a predefined white list or black list.

Abstract: The operational continuity of a programmable device, and a controller using the same is enhanced.

Abstract: A packet collection system for collecting a packet for abnormality detection in a communication system including segments in which a packet having an encrypted payload is transmitted and received.

Abstract: The operational continuity of a programmable device, and a controller using the same is enhanced.

Abstract: A communication control system includes: a state switching support apparatus including a processor; and a communication control apparatus to control communication to a protection target according to its state. The processor executes generating grid point data in which a grid point group representing exhaustive communications to the target is associated with states corresponding to grid points of the grid point group using previously collected data related to the communication; generating, by using the grid point data and data related to current communication, generating a state distribution representing a distribution of the states in a vicinity of a point represented by the data related to current communication in the grid point group; predicting a time when the state transitions to another state from a change in the state distribution from past to present; and transmitting an instruction to switch the state to the communication control apparatus at the predicted time.

Abstract: A signal transmission device has a multi-point wiring structure in which termination resistors are mounted on both ends of a cable, and a plurality of PCBs connected to the cable transmit a signal through the cable. The PCB of a host node includes: a connector connected to the cable; a transformer unit that is connected to the connector via a first PCB transmission line and insulates the connector; an RS 485 transceiver that is connected to the transformer unit via a second PCB transmission line and transmits the signal to the PCB of another node or receives the signal from the PCB of another node; and AC termination that is provided in at least one of the first PCB transmission line and the second PCB transmission line and suppresses resonance and antiresonance in a reflection frequency characteristic of noise.

Abstract: A signal transmission device has a multi-point wiring structure in which termination resistors are mounted on both ends of a cable, and a plurality of PCBs connected to the cable transmit a signal through the cable. The PCB of a host node includes: a connector connected to the cable; a transformer unit that is connected to the connector via a first PCB transmission line and insulates the connector; an RS 485 transceiver that is connected to the transformer unit via a second PCB transmission line and transmits the signal to the PCB of another node or receives the signal from the PCB of another node; and AC termination that is provided in at least one of the first PCB transmission line and the second PCB transmission line and suppresses resonance and antiresonance in a reflection frequency characteristic of noise.

Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.

Abstract: A vehicle includes: a power source; a first drive device configured to be driven by an output of the power source; a second drive device configured to be driven by the output of the power source; a non-stage transmission device capable of continuously changing a rotation speed which is transmitted to an input shaft of the second drive device; a power distribution device coupled to an output shaft of the power source, coupled to an input shaft of the first drive device and an input shaft of the non-stage transmission device, and configured to be capable of distributing the output of the power source to the first drive device and the second drive device in a state where the output shaft of the power source is coupled to the input shaft of the first drive device and the input shaft of the non-stage transmission device at respective predetermined fixed reduction ratios; a first instruction device configured to output a first instruction value related to a rotation speed of the input shaft of the first drive devic

Abstract: Provided is a semiconductor LSI design device that includes: a unit that generates a combinational circuit constituted by combining function blocks defined by a function block library from an application specification, by assigning connection information on an operation order of the function blocks; a unit that converts the combinational circuit to operation order information that is applicable to a sequential circuit in which a function block is used a plurality of times in a time-division manner; a unit that inversely converts the generated operation order information to a combinational circuit; a unit that verifies logical equivalence of the combinational circuit and the inversely converted combinational circuit; and a unit that combines the operation order information, the sequential circuit and a function block.

Abstract: Provided is a semiconductor LSI design device that includes: a unit that generates a combinational circuit constituted by combining function blocks defined by a function block library from an application specification, by assigning connection information on an operation order of the function blocks; a unit that converts the combinational circuit to operation order information that is applicable to a sequential circuit in which a function block is used a plurality of times in a time-division manner; a unit that inversely converts the generated operation order information to a combinational circuit; a unit that verifies logical equivalence of the combinational circuit and the inversely converted combinational circuit; and a unit that combines the operation order information, the sequential circuit and a function block.

Abstract: The present invention includes a drawing data generating unit, a variation pattern that varies at regular intervals to be displayed, a display unit that displays drawing data, and a comparator that compares whether input signals are coincident, and the drawing data generating unit includes a receiver that receives data from a higher-level device, a drawing control unit that converts the data received from the higher-level device to drawing data, and a drawing memory that stores the drawing data. The drawing data generating unit and the variation pattern are redundantly configured, and the variation pattern is input to the drawing data generating unit. One output signal of the drawing data generating unit regarding drawing data including the variation pattern is transmitted to the display unit, a plurality of output signals from the drawing data generating unit are input to the comparator, and the comparator outputs a comparison result as a detection signal outside.

Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.

Abstract: A control system includes an arithmetic device configured of an A system arithmetic unit including a data dividing unit, a B system arithmetic unit including a data dividing unit, and an A system communication control unit including a data combining unit and a collation unit, wherein the A system arithmetic unit and the B system arithmetic unit have a duplex configuration, the A system arithmetic unit and the B system arithmetic unit are separated by a gap, a frame output from the A system arithmetic unit is transmitted to a B system communication control unit through the A system communication control unit and an interface element, and a frame output from the B system arithmetic unit is transmitted to the A system communication control unit through the B system communication control unit and an interface element.

Abstract: A vehicle includes: a power source; a first drive device configured to be driven by an output of the power source; a second drive device configured to be driven by the output of the power source; a non-stage transmission device capable of continuously changing a rotation speed which is transmitted to an input shaft of the second drive device; a power distribution device coupled to an output shaft of the power source, coupled to an input shaft of the first drive device and an input shaft of the non-stage transmission device, and configured to be capable of distributing the output of the power source to the first drive device and the second drive device in a state where the output shaft of the power source is coupled to the input shaft of the first drive device and the input shaft of the non-stage transmission device at respective predetermined fixed reduction ratios; a first instruction device configured to output a first instruction value related to a rotation speed of the input shaft of the first drive devic

Abstract: A motor that rotates an annular member includes a stationary portion including a stator, and a rotating portion arranged to be rotatable about a central axis extending in a vertical direction. The rotating portion includes a hub extending in an annular shape around the central axis; a magnet including a pole surface arranged radially opposite to the stator; and a yoke to which the magnet is fixed. The yoke includes a yoke increased thickness portion arranged radially outside of the magnet; and a yoke decreased thickness portion with a radial thickness smaller than that of the yoke increased thickness portion, and arranged axially above the yoke increased thickness portion. The yoke decreased thickness portion is fixed to the hub annular portion through press fitting.

Abstract: A control system includes an arithmetic device configured of an A system arithmetic unit including a data dividing unit, a B system arithmetic unit including a data dividing unit, and an A system communication control unit including a data combining unit and a collation unit, wherein the A system arithmetic unit and the B system arithmetic unit have a duplex configuration, the A system arithmetic unit and the B system arithmetic unit are separated by a gap, a frame output from the A system arithmetic unit is transmitted to a B system communication control unit through the A system communication control unit and an interface element, and a frame output from the B system arithmetic unit is transmitted to the A system communication control unit through the B system communication control unit and an interface element.

Abstract: This motor is arranged to rotate an annular member, and includes a stationary portion including a stator, and a rotating portion arranged to be rotatable about a central axis extending in a vertical direction. The rotating portion includes a hub arranged to extend in an annular shape around the central axis; a magnet including a pole surface arranged radially opposite to the stator; and a yoke to which the magnet is fixed. The hub includes a hub annular portion in the shape of a circular ring and arranged above the stator, and a flange surface on which the annular member is arranged. The yoke includes a yoke increased thickness portion arranged radially outside of the magnet; and a yoke decreased thickness portion arranged to have a radial thickness smaller than that of the yoke increased thickness portion, and arranged axially above the yoke increased thickness portion. The yoke decreased thickness portion is fixed to the hub annular portion through press fitting.

Abstract: Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.