Abstract: In a debugging microprocessor having a function of elongating a bus cycle in response to an external ready signal and used in a microprocessor development support system having a function capable of tracing and analyzing the result of execution, there is provided a generator for generating a bus cycle end signal for the microprocessor development support system. The generator comprises a ready detection circuit receiving an external ready signal, a clock signal and an enable signal which is rendered active only when the debugging microprocessor is in a condition capable of accepting data. The ready detection circuit operates to detect the status of the external ready signal at a time defined by a clock appearing when the enable signal is active, so as to generate an internal ready signal if the external ready signal is active.

Abstract: An in-circuit emulator is inserted in a CPU socket of a target system that uses a program designed to use virtual addresses. The in-circuit emulator includes a first emulation processor for emulating execution of the program of the target system, a second emulation processor having the same arrangement as that of the first emulation processor, for outputting a virtual address corresponding to a physical address output from the first emulation processor, and a means for outputting a break request signal when a virtual address at a desired breakpoint in the program and the output virtual address do not coincide with each other.

Abstract: A debugging microprocessor used in an in-circuit emulator is made to be capable of moving into a debugging interrupt processing execution mode in response to an external supervisor interrupt instruction. This debugging microprocessor comprises a first program counter put in an operating condition when the microprocessor is in a user's program execution mode, a second program counter put in an operating condition when the microprocessor is in a debugging interrupt processing execution mode, and a program counter controller responding to the external supervisor interrupt instruction to cause a content of the second program counter to be outputted as a program counter value. The program counter controller also responds to a return instruction to cause a content of the first program counter to be outputted as a program counter value. Thus, the content of the first program counter can be accessed in the course of the debugging interrupt processing execution.

Abstract: A debugging processor includes a bus control unit for transmitting and receiving data to and from an external, an instruction execution unit receiving an instruction code from the bus control unit for executing the given instruction, and an interrupt control unit for notifying the instruction execution unit of an interrupt request. The debugging processor also comprises a debug interrupt response control unit having a priority higher than that of the interrupt control unit and having a fixed branch destination address. This debug interrupt response control unit operates to generate to the external a debug interrupt response signal which becomes active during a period of save operation for an internal information.