Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

Abstract: A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refresh command and reproduces read data by using the second memory block. When a write command and the refresh command conflict with each other, a write control circuit operates the memory block according to an order of command reception. Therefore, it is possible to perform refresh operation without being recognized by users. Namely, a user-friendly semiconductor memory can be provided.

Abstract: According to the present invention, in an integrated circuit device for receiving an external clock signal and a clock enable signal and for supplying to an internal circuit an internal clock signal which has a predetermined phase relationship with the external clock signal, a DLL circuit for generating a delay clock signal, synchronized and in phase with the external clock signal, is operated continuously even in a low power consumption mode, and the provision of the delay clock signal to the internal circuit is halted. When the mode is switched from the low power consumption mode to the normal mode, the delay clock signal generated by the DLL circuit, which is operated continuously, is supplied as an internal clock signal to the internal circuit again.