Patents by Inventor Masahisa Kimura

Masahisa Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6690245
    Abstract: An oscillation control circuit is offered which can improve the startability of an oscillator circuit operating at high frequencies and at a low power-supply voltage. When the oscillation potential of the oscillation signal is between the inversion potential (1.2 volts) of a CMOS inverter IV1 and the inversion potential (1.8 volts) of a CMOS inverter IV2, the logical output value of a CMOS Schmitt inverter SI1 is 1. The output of a CMOS inverter formed by MOS transistors T32 and T33 is shorted out via a MOS transistor T34. Its logical output value is kept at 1. When the inversion potential of the CMOS inverter IV1 or the inversion potential of the CMOS inverter IV2 is exceeded, if the input voltage to the CMOS Schmitt trigger SI1 increases above its inversion potential (1.8 volts), the logical output value assumes a value of 0. The CMOS inverter formed by the MOS transistors T12 and T13 is first set into operation. The oscillation signal is inverted, setting a circuit LA at a later stage into operation.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: February 10, 2004
    Assignee: Nippon Precision Circuits Inc.
    Inventors: Eiichi Hasegawa, Kazuhisa Oyama, Masahisa Kimura
  • Patent number: 6556094
    Abstract: An oscillator circuit adapted for a piezoelectric oscillator which has a weak oscillation output for generating high frequencies is provided. The speed of operation of the oscillator circuit is increased. An integrated circuit for such an oscillator circuit is also provided. The oscillator circuit has an amplifier portion consisting of CMOS inverters connected in cascade. MOS transistors forming the CMOS inverters have channel widths that decrease successively from the first stage to the last stage to improve the amplification factor of the amplifier portion at high frequencies. This makes it possible to amplify weak oscillation output from the quartz oscillator (XL). A filter circuit produces a peak of negative resistance at a frequency higher than conventional. This permit oscillation operation at higher frequencies.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: April 29, 2003
    Assignee: Nippon Precision Circuits Inc.
    Inventors: Eiichi Hasegawa, Masahisa Kimura, Kazuhisa Oyama, Kunihiko Tsukagoshi
  • Publication number: 20020125965
    Abstract: An oscillator circuit adapted for a piezoelectric oscillator which has a weak oscillation output for generating high frequencies is provided. The speed of operation of the oscillator circuit is increased. An integrated circuit for such an oscillator circuit is also provided. The oscillator circuit has an amplifier portion consisting of CMOS inverters connected in cascade. MOS transistors forming the CMOS inverters have channel widths that decrease successively from the first stage to the last stage to improve the amplification factor of the amplifier portion at high frequencies. This makes it possible to amplify weak oscillation output from the quartz oscillator (XL). A filter circuit produces a peak of negative resistance at a frequency higher than conventional. This permit oscillation operation at higher frequencies.
    Type: Application
    Filed: October 26, 2001
    Publication date: September 12, 2002
    Inventors: Eiichi Hasegawa, Masahisa Kimura, Kazuhisa Oyama, Kunihiko Tsukagoshi
  • Publication number: 20020075090
    Abstract: An oscillation control circuit is offered which can improve the startability of an oscillator circuit operating at high frequencies and at a low power-supply voltage. When the oscillation potential of the oscillation signal is between the inversion potential (1.2 volts) of a CMOS inverter IV1 and the inversion potential (1.8 volts) of a CMOS inverter IV2, the logical output value of a CMOS Schmitt inverter SI1 is 1. The output of a CMOS inverter formed by MOS transistors T32 and T33 is shorted out via a MOS transistor T34. Its logical output value is kept at 1. When the inversion potential of the CMOS inverter IV1 or the inversion potential of the CMOS inverter IV2 is exceeded, if the input voltage to the CMOS Schmitt trigger SI1 increases above its inversion potential (1.8 volts), the logical output value assumes a value of 0. The CMOS inverter formed by the MOS transistors T12 and T13 is first set into operation. The oscillation signal is inverted, setting a circuit LA at a later stage into operation.
    Type: Application
    Filed: November 29, 2001
    Publication date: June 20, 2002
    Inventors: Eiichi Hasegawa, Kazuhisa Oyama, Masahisa Kimura